MCP33131 datasheet(4/54 Pages) MICROCHIP

4 / 54 page

DS20006122A-page 4

 2018 Microchip Technology Inc.

MCP33131/MCP33121/MCP33111-XX

Analog Inputs

Input Voltage Range

VIN+

-0.1

—

VREF+0.1

(Note 2)

Input Full-Scale Voltage Range

FSR

—

+VREF

VPP

(Note 2)

Input Sampling Capacitance

—31

—

(Note 1)

-3dB Input Bandwidth

BW-3dB

—25

—

MHz

(Note 1)

Aperture Delay

(Note 1)

—

2.5

—

Time delay between CNVST rising

edge and when input is sampled

Leakage Current at Analog Input Pin

ILEAK_AN_INPUT

—

±2

±200

During input acquisition (tACQ)

System Performance

Sample Rate

(Throughput rate)

—

Msps

MCP331x1-10

—

500

kSPS

MCP331x1-05

Resolution

(No Missing Codes)

—

Bits

MCP33131-10 and MCP33131-05

—

Bits

MCP33121-10 and MCP33121-05

—

Bits

MCP33111-10 and MCP33111-05

Integral Nonlinearity

INL

-6

±2.2

LSB

MCP33131-10 and MCP33131-05

-1.5

±0.55

+1.5

LSB

MCP33121-10 and MCP33121-05

±0.12

LSB

MCP33111-10 and MCP33111-05

Differential Nonlinearity

DNL

-0.98

±0.9

+1.8

LSB

MCP33131-10 and MCP33131-05

-0.8

±0.25

+0.8

LSB

MCP33121-10 and MCP33121-05

-0.3

±0.06

+0.3

LSB

MCP33111-10 and MCP33111-05

Offset Error

±0.1

±2.3

MCP33131-10 and MCP33131-05

—

±0.125

±3

MCP33121-10 and MCP33121-05

—

±0.8

±3.66

MCP33111-10 and MCP33111-05

Offset Error Drift with Temperature

—

±0.8

—

V/oC

Gain Error

GER

—

±4

—

LSB

MCP33131-10 and MCP33131-05

—

±1

—

LSB

MCP33121-10 and MCP33121-05

—

±0.2

—

LSB

MCP33111-10 and MCP33111-05

Gain Error Drift with temperature

—

±0.35

—

V/oC

Input Common-Mode

Rejection Ratio

CMRR

—

Power Supply Rejection Ratio

PSRR

—

(Note 4)

TABLE 1-1:

KEY ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF =5V,

GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN =10 kHz, CLOAD_SDO = 20 pF.

• MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.

• MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Note

1: This parameter is ensured by design and not 100% tested.

2: This parameter is ensured by characterization and not 100% tested.

3: Decoupling capacitor is recommended on the following pins:

(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.

4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.

5: ENOB = (SINAD - 1.76)/6.02

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