MCP33131 datasheet(30/54 Pages) MICROCHIP

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DS20006122A-page 30

 2018 Microchip Technology Inc.

MCP33131/MCP33121/MCP33111-XX

6.0

DEVICE OVERVIEW

The device converts unipolar single-ended analog

input into unipolar straight binary codes.

When the MCP33131/MCP33121/MCP33111-XX is

first powered-up, it performs a self-calibration and

enters a low current input acquisition mode (Standby)

by itself.

The external reference voltage (VREF) ranging from

2.5V to 5.1V sets the input full-scale range (FSR) from

0V to +VREF.

During input acquisition (Standby), the internal input

sampling capacitors are connected to the input signal,

while most of the internal analog circuits are shutdown

to save power. During this input acquisition time

(tACQ), the device consumes less than 1 A.

The user can operate the device with an easy-to-use

SPI-compatible 3-wire interface.

The device initiates data conversion on the rising edge

of the conversion-start control (CNVST). The data con-

version time (tCNV) is set by the internal clock. Once

the conversion is complete, the device starts the next

input acquisition. During this input acquisition time

(tACQ), the user can clock out the output data by pro-

viding the external SPI serial clock (SCLK).

The device provides conversion data with no missing

codes. This ADC device family has a large input

full-scale range, high precision, high throughput with

no output latency, and is an ideal choice for various

ADC applications.

6.1

Analog Input

Figure shows a simplified equivalent circuit of the

input architecture with a switched capacitor input stage.

The input sampling capacitor (CS+) is about 31 pF. The

back-to-back diodes (D1 - D2) at each input pin are

ESD protection diodes. Note that these ESD diodes are

tied to VREF, so that each input signal can swing from

0V to VREF.

The input sampling and hold circuit in AIN+ path is also

repeated in AIN- path. This allows the device to perform

a pseudo-differential conversion of the input signal.

Therefore, the common mode signal presented at both

input pins is rejected. In applications, AIN+ pin is for the

input signal and AIN- pin is for the ground reference of

the input signal. The user must connect the AIN- pin to

a clean ground plane of the input signal externally.

During input acquisition phase (Standby), the sampling

switches are closed and each input sees the sampling

capacitor (≈ 31 pF) in series with the on-resistance of

the sampling switch, RSON (≈ 200).

For high-precision data conversion applications, the

input voltage needs to be fully settled within 1/2 LSB

during the input acquisition period (tACQ). The settling

time is directly related to the source impedance: A

lower impedance source results in faster input settling

time. Although the device can be driven directly with a

low impedance source, using a low noise input driver is

highly recommended.

Simplified Equivalent Analog Input Circuit.

Note:

The ESD diodes at the analog input pins

are biased from VREF. Any input voltage

outside the absolute maximum range can

turn on the input ESD protection diodes

and results in input leakage current which

may

cause

conversion

errors

and

permanent damage to the device. Care

must be taken in setting the input voltage

ranges so that the input voltage does not

exceed the absolute maximum input

voltage range.

VT = 0.6V

VREF

ILEAKAGE

(~ ±1 nA)

AIN+

MCP331x1-XX

RSON

CPIN

RSON = On-resistance of the sampling switch ≈ 200 

= Package pin + ESD capacitor ≈ 2 pF.

where:

CS+ , CS- = Input sample and hold capacitor ≈ 31 pF.

AIN-

(200

)

SW1+

SW2+

(31 pF)

AIN+ = Analog input.

AIN- = Ground reference of analog input.

Sample VIN+

VT = 0.6V

VREF

ILEAKAGE

(~ ±1 nA)

CPIN

RSON

(200

)

SW1-

SW2-

(31 pF)

Sample VIN-

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