MCP33131 datasheet(29/54 Pages) MICROCHIP

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DS20006122A-page 29

MCP33131/MCP33121/MCP33111-XX

5.0

PIN FUNCTION DESCRIPTIONS

TABLE 5-1:

PIN FUNCTION TABLE

5.1

Supply Voltages (AVDD, DVIO)

The device has two power supply pins:

(a) Analog power supply (AVDD): 1.8V

(b) Digital input/output interface power supply (DVIO):

1.7V to 5.5V.

The large supply voltage range of DVIO allows the

device to interface with various host devices that are

operating with different supply voltages. See Table 1-2

for timing specifications for I/O interface signal

parameters depending on DVIO voltage.

5.2

Reference Voltage (VREF)

The device requires a single-ended external reference

voltage (VREF). The external input reference range is

from 2.5V to 5.1V. This reference voltage sets the

input full-scale range from 0V to VREF. See Figure 6-1

to Figure 6-2 for example application circuit and

reference voltage settings.

5.2.1

VOLTAGE REFERENCE

SELECTION

The performance of the voltage reference has a large

impact on the accuracy of high-precision data

acquisition systems. The voltage reference should

have high-accuracy, low-noise, and low-temperature

drift. A ±0.1% output accuracy of the reference directly

corresponds to ±0.1% absolute accuracy of the ADC

output. The RMS output noise voltage of the reference

should be less than 1/2 LSB of the ADC.

Pin Number

Pin Name

Function

VREF

Reference voltage input (2.5V - 5.1V).

This pin should be decoupled with a 10

F tantalum capacitor.

2AVDD

DC supply voltage input for analog section (1.8V).

This pin should be decoupled with a 1

F ceramic capacitor.

3AIN+

Analog input.

4AIN-

Ground reference pin for analog input. Connect this pin to the ground reference of the

analog input.

GND

Power supply ground reference. This pin is a common ground for both the analog

power supply (AVDD) and digital I/O supply (DVIO).

CNVST

Conversion-start control and active-low SPI chip-select digital input.

A new conversion is started on the rising edge of CNVST.

When the conversion is complete, output data is available at SDO by lowering CNVST.

SDO

SPI-compatible serial digital data output: ADC conversion data is shifted out by SCLK

clock, with MSB first.

SCLK

SPI-compatible serial data clock digital input.

The ADC output is synchronously shifted out by this clock.

SDI

SPI-compatible serial data digital input. Tie to DVIO for normal operation.

DVIO

DC supply voltage for digital input/output interface (1.7V - 5.5V).

This pin should be decoupled with a 0.1

F ceramic capacitor.

Note:

Proper decoupling capacitors (1

F to

AVDD, 0.1 F to DVIO) should be mounted

as close as possible to the respective

pins. See Figure 6-1 for example circuit.

Note:

The reference pin needs a tantalum

decoupling capacitor (10

F, 10V rating).

Additional multiple ceramic capacitors can

be added in

parallel

decouple

high-frequency noises.

Note:

During the initial power-up sequence, the

reference

voltage

(VREF) must be

provided prior to supplying AVDD or within

about 64 ms after supplying AVDD.

Otherwise, it is strongly recommended to

send

recalibrate

command.

See

Section 7.1 “Recalibrate Command” for

more details.

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