INA229 datasheet(19/48 Pages) TI

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– MISO - SPI Secondary Out / Main In data (tri-state output)

• The SPI frame size is variable in length depending on the INA229-Q1 register accessed through the SPI

interface as following:

– Main to Secondary (MOSI): 6 bits for register Address; 1 bit low; 1 R/W bit (read / not write); variable

length of low bits depending on the INA229-Q1 register length.

– Secondary to Main (MISO): 8 bits low; variable length of bits depending on the INA229-Q1 register length.

• SPI bit-speed up to 10 Mbit/s

• Both Main commands and INA229-Q1 data are shifted MSB first, LSB last

• The data on the MOSI line is sampled on the falling edge of SCLK

• The data on the MISO line is shifted out on the rising edge of SCLK

The SPI communication starts with the CS falling edge, and ends with CS rising edge. The CS high level keeps

secondary SPI interface in an idle state, and MISO output is tri-stated.

Since the MISO output is push-pull it is ideal to have the INA229-Q1 supply at the same voltage as the primary

device I/O supply. If different supply voltages are used, level translation is recommended.

7.5.1.1 SPI Frame

SPI communication to the INA229-Q1 device is performed through register address access. Communication to

every register starts with a 6-bit register address followed by a "0" and a R/W bit. Setting the R/W bit to "1"

indicates that the current SPI frame will read from a device register while setting the R/W bit to "0" indicates the

current SPI frame will write data to a device register.

MISO

MOSI

ADDR

DATA

MSB

DATA

LSB

. . . .

. . . . . .

16 ± 40 bits

SCLK

Figure 7-7. SPI Read Frame

SCLK

MISO

MOSI

ADDR

DATA

MSB

DATA

LSB

. . . . . .

. . . .

16 bits

DATA

MSB

DATA

LSB

. . . .

. . . . .

Figure 7-8. SPI Write Frame

Note that while the read frame can be variable in length due to the different length registers in the INA229-Q1

device, the write frame is fixed in length as all writable registers are 16 bits wide. During an SPI write frame,

while new data is shifted into the INA229-Q1 register, the old data from the same register is shifted out on the

MISO line.

The first 8-bits of each SPI frame are presented in Table 7-2, which shows access to a certain register address

on the MOSI line as well as read/write functionality. On an SPI read operation, the INA229-Q1 returns the data

read in the same SPI frame.

www.ti.com

INA229-Q1

SLYS024A – MAY 2020 – REVISED JUNE 2021

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