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INA229 датащи(PDF) 7 Page - Texas Instruments

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номер детали INA229
подробное описание детали  INA229-Q1 AEC-Q100, 85-V, 20-Bit, Ultra-Precise Power/Energy/Charge Monitor With SPI Interface
PDF  48 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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INA229 датащи(HTML) 7 Page - Texas Instruments

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6.6 Timing Requirements (SPI)
MIN
NOM
MAX
UNIT
SERIAL INTERFACE
fSPI
SPI bit frequency
10
MHz
tSCLK_H
SCLK high time
40
ns
tSCLK_L
SCLK low time
40
ns
tCSF_SCLKR
CS fall to first SCLK rise time
10
ns
tSCLKF_CSR
Last SCLK fall to CS rise time
10
ns
tFRM_DLY
Sequential transfer delay (1)
50
ns
tMOSI_RF
MOSI Rise and Fall time, 10 MHz SCLK
15
ns
tMOSI_ST
MOSI data setup time
10
ns
tMOSI_HLD
MOSI data hold time
20
ns
tMISO_RF
MISO Rise and Fall time, CLOAD = 200 pF
15
ns
tMISO_ST
MISO data setup time
20
ns
tMISO_HLD
MISO data hold time
20
ns
tCS_MISO_DLY
CS falling edge to MISO data valid delay time
25
ns
tCS_MISO_HIZ
CS rising edge to MISO high impedance delay time
25
ns
(1)
Optional. The SPI interface can operate without the CS pin assistance as long as the pin is held low.
6.7 Timing Diagram
tSCLK_L
High-Z
High-Z
CS
SCLK
MOSI
MISO
X
undefined
undefined
MSB
MSB
LSB
LSB
tSCLK_H
tSCLKF_CSR
tCSF_SCLKR
tFRM_DLY
tMOSI_RF
tMISO_RF
tMOSI_ST
tMOSI_HLD
tMISO_ST
tCS_MISO_DLY
tMISO_HLD
tCS_MISO_HIZ
tSCLK_L
Figure 6-1. SPI Timing Diagram
www.ti.com
INA229-Q1
SLYS024A – MAY 2020 – REVISED JUNE 2021
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: INA229-Q1



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