MCP3461 datasheet(76/108 Pages) MICROCHIP

76 / 108 page

MCP3461/2/4

DS20006180D-page 76

 2019-2021 Microchip Technology Inc.

6.8.4

CRCCFG ERROR INTERRUPT

The CRCCFG interrupt happens when an error in the

CRC-16 checksum has been detected in the register

map CRC calculation.

This interrupt is implemented with three different and

independent mechanisms: STATUS byte on SDO, IRQ

6.8.4.1

STATUS Byte on SDO

When the CRCCFG error happens, on the next STATUS

byte transmitted on SDO, the CRCCFG_STATUS bit will

be logic low. Once the STATUS byte has been transmit-

ted, the CRCCFG_STATUS bit will then appear as ‘1’

until a new interrupt occurs. If between two STATUS byte

transmissions, the error is detected once again, the

CRCCFG_STATUS bit on SDO will appear as equal to

‘0’ on the second reading.

6.8.4.2

IRQ Register Status Bit

When

the

CRCCFG

error

happens,

the

CRCCFG_STATUS bit in the IRQ register will be set to

‘0’. Once the IRQ register has been fully read, this

CRCCFG_STATUS bit will be reset back to ‘1’. If

between two readings of the IRQ register, the

CRCCFG error happens once again, the IRQ register

Status bit will appear as ‘0’ on the second reading.

6.8.4.3

IRQ Pin State

The CRCCFG error generates a Logic Low state on the

IRQ pin until it is cleared. The clearing of the CRCCFG

error can only be made by “unlocking” the device (by

writing 0xA5 in the LOCK[7:0] register or by sending a

Fast

command

start/restart ADC

conversion).

Unlocking the device stops the CRC calculation and

clears the associated interrupt. Sending an ADC

start/restart conversion Fast command resets the CRC

calculation and clears the interrupt as well.

This CRCCFG error can only happen in case of an

external perturbation (for example, EMI induced) that

would cause the continuous calculation of the CRC on

the register map to be erroneous or in the case that the

chip integrity has been altered. Since both causes are

high-priority issues, the CRCCFG error takes priority

over all other interrupts (except POR) and over the

MDAT output on the IRQ pin.

Note:

If MCLK is running before the device has

been locked, an interrupt can momentarily

occur even if registers have not been

corrupted. In such a case, the user needs

to send a start/restart conversion Fast

command, which will clear the unwanted

interrupt and correctly restart the CRC

calculations.

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