MCP3461 datasheet(36/108 Pages) MICROCHIP

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MCP3461/2/4

DS20006180D-page 36

 2019-2021 Microchip Technology Inc.

5.3.2

DIGITAL GAIN

When the gain setting is chosen from 16x to 64x, the

analog gain stays constant at 16x and the additional

gain is done in the digital domain by a simple shift and

round of the output code. The digital gain range is 1x to

4x. The output noise is approximately unchanged (out-

side from the quantization noise that is slightly

decreased). The SNR is thus degraded by 6 dB per

octave from the 16x to 64x setting.

This digital gain is useful to scale-up the signals without

using the host device (MCU) operations, but they

degrade SNR and resolution (1 bit per octave) and do

not significantly improve the noise performance, except

for very large OSR settings.

5.4

Delta-Sigma Modulator

5.4.1

ARCHITECTURE

The Sigma-Delta

 ADC includes a second-order

modulator with a multibit DAC architecture. Its 5-level

quantizer is a Flash ADC composed of four compara-

tors with equally spaced thresholds and a thermometer

output coding. The proprietary 5-level architecture

ensures minimum quantization noise at the outputs of

the modulators without disturbing linearity or inducing

additional distortion.

Unlike most multibit DAC architectures, the 5-level

DAC used in this architecture is inherently linear, and

therefore, does not degrade the ADC linearity and THD

performance.

The sampling frequency is DMCLK; therefore, the

modulator outputs are refreshed at a DMCLK rate.

Figure 5-2 represents a simplified block diagram of the

Delta-Sigma modulator.

FIGURE 5-2:

Simplified Delta-Sigma ADC

Block Diagram.

5.4.2

MODULATOR OUTPUT BLOCK

The modulator output option allows users to apply their

own digital filtering on the output bit stream. By setting

IRQ_MODE[1] = 1 in the IRQ register, the modulator

output is available at the IRQ/MDAT pin, at the AMCLK

rate and through the ADCDATA register (0x0) with

DMCLK rate. With this configuration, the digital deci-

mation filter is disabled in order to reduce the current

consumption and no data ready interrupt is generated

on any of the IRQ mechanisms. The IRQ/MDAT pin is

never placed in high-impedance during the Modulator

Output mode.

Since the Delta-Sigma modulator has a 5-level output

given by the state of four comparators with thermometer

coding, the output is represented using four bits, each bit

represents the state of the corresponding comparator

(see Table 5-4).

The comparator output bits are arranged serially at the

AMCLK rate on the IRQ/MDAT output pin (see

Figure 5-3).

This 1-bit serial bit stream is considered to be the same

one as it is produced by a 1-bit DAC modulator with a

sampling frequency of AMCLK. The modulator can

either be considered as a 5 level-output at DMCLK rate

or as 1-bit output at AMCLK rate. These two represen-

tations are interchangeable. The MDAT outputs can

therefore be used in any application that requires 1-bit

modulator outputs. This application can be integrated

with an external sinc filter or more advanced decima-

tion filters that are computed in the MCU or DSP

device.

When CLK_SEL[1:0] = 11 (internal oscillator with

external clock output), the AMCLK clock is present on

the MCLK pin. This configuration permits correctly

synchronizing the bit stream when the internal

oscillator is used as the master clock source.

When CLK_SEL[1:0] = 00, the modulator outputs are

also synchronized with the MCLK input, but the ratio

between MCLK and AMCLK needs to be taken into

account in the user applications to correctly retrieve the

desired bit stream.

The default value of the bit stream after a Reset or a

power-up is ‘0011’. It is equivalent to a 0V input for the

ADC. After each ADC Reset and restart (see

Section 5.15 “A/D Conversions Automatic Reset

and Restart Feature”), the bit stream output is also

reset and restarted and the IRQ/MDAT is kept equal to

logic high during the two MCLK clock periods needed

for the synchronization. After these two clock periods,

the bit stream will be provided on the IRQ/MDAT pin

and the first value will be the default value.

Differential Input

Voltage

(from Analog Mux)

Analog

nd Order

Loop

Filter

Output

Bitstream

Thermometer Coding

(to Digital Filter)

Delta-Sigma 2

nd Order 5-Level Modulator

Analog

Digital

5-Level DAC

Quantizer

5-Level Flash

ADC

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