MCP3461 datasheet(72/108 Pages) MICROCHIP

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MCP3461/2/4

DS20006180D-page 72

 2019-2021 Microchip Technology Inc.

6.8

Interrupts Description

The MCP3461/2/4 devices incorporate multiple interrupt

mechanisms to be able to synchronize the device with

an MCU and to warn against external perturbations.

There are four events that can generate interrupt flags:

• Conversion Start

• Data Ready

• Power-on Reset

• CRC Error on the Register Map Configuration

Additionally, there are three independent interrupt

mechanisms that allow the devices to be implemented

in many different applications and many different con-

figurations. A summary of the different mechanisms is

available in Table 6-2.

TABLE 6-2:

INTERRUPT DESCRIPTION SUMMARY TABLE

Interrupt Flag Type

Description

Clearing Procedure

STATUS Byte

Three status bits (DR_STATUS,

CRCCFG_STATUS, POR_STATUS) are

latched together after device address

detection and are clocked out during each

command on the SDO STATUS byte.

Cleared when STATUS byte clocking is finished

(on the last SCK falling edge).

IRQ Register Status

Bits

IRQ register Status bits can be read when

reading the address 0x5 (IRQ register).

IRQ latching happens at the beginning of

the IRQ register reading.

Cleared when the IRQ register reading is

finished (on the last SCK falling edge).

IRQ Pin State

• When IRQ_MODE[1] = 0: The IRQ

pin can be asserted to logic low by

any of the interrupts.

• When IRQ_MODE[1] = 1: Only POR

and CRC interrupts can assert the

IRQ pin to logic-low.

• Conversion start interrupt is cleared

automatically at the beginning of a new

conversion cycle after a TSTP timing.

• DR interrupt is cleared by the first SCK

falling edge of an ADC read or automatically

16 DMCLK periods before a new data ready

in Continuous Conversion mode or in SCAN

mode.

• POR interrupt is cleared on the first CS

falling edge when both AVDD and DVDD

monitoring circuits are detecting their power

supply to be over their respective

thresholds.

• CRCCFG interrupt is cleared when the

device is unlocked (writing 0xA5 to LOCK

start/restart conversion is performed.

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