MCP3461 datasheet(49/108 Pages) MICROCHIP

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DS20006180D-page 49

MCP3461/2/4

5.11.3

INTERNAL MASTER CLOCK

MODES (CLK_SEL[1:0] = 1x)

When CLK_SEL[1] = 1, the internal oscillator is

selected and the master clock is generated internally.

The internal oscillator has no Reset feature and is

always running once selected. The master clock

generation is independent of the ADC, as the clock can

still be generated even if the ADC is in ADC Shutdown

mode. The internal oscillator is only disabled when

CLK_SEL[1:0] = 0x. The clock can be distributed to the

dedicated output pin depending on the CLK_SEL[0] bit.

When the clock output is selected (CLK_SEL[0] = 1),

the AMCLK

clock

derived

from

the

MCLK

(AMCLK = MCLK/PRESCALE) is available on the out-

put pin. The AMCLK output can serve as the clock pin

to synchronize either the modulator output or other

MCP3461/2/4 devices that would be configured with

CLK_SEL[1:0] = 00 or 01.

The AMCLK output is available on the MCLK clock

output pin as soon as the Write command

(CLK_SEL[1:0] = 11) is finished.

5.12

Digital System Offset and Gain

Calibrations

The MCP3461/2/4 devices include a digital calibration

feature for offset and gain errors. The calibration

scheme for offset error consists of the addition of a

fixed offset value to the ADC output code (ADCDATA at

address 0x0). The offset value added (OFFSETCAL) is

determined in the OFFSETCAL register (address: 0x9).

The calibration scheme for gain error consists of the

multiplication of a fixed gain value to the ADC output

code. The gain value (GAINCAL) multiplied is

determined in the GAINCAL register (address 0xA).

The digital offset and gain calibration schemes are

enabled or disabled via the EN_OFFCAL and

EN_GAINCAL control bits of the CONFIG3 register.

When both calibration control bits are enabled

(EN_OFFCAL = EN_GAINCAL = 1), the ADCDATA

gain calibration schemes, as described in Equation 5-6.

When a calibration enable bit is off, its corresponding

corresponding calibration is not performed.

EQUATION 5-6:

ADCDATA OUTPUT

AFTER DIGITAL GAIN

AND OFFSET ERROR

CALIBRATION

The calculations are performed internally with proper

management of overloading, so that the overload

detection is done on the output result only and not on

the intermediate results. A sufficient number of addi-

tional overload bits are maintained and propagated

internally to overcome all possible overload and/or

overload recovery situations.

For example, if ADCDATA (pre-calibration) + OFFSETCAL

is out of bounds but (ADCDATA (pre-calibration) +

OFFSETCAL) * GAINCAL is still in the right range

(possible with 0 < GAINCAL < 1), then the result is not

saturated.

5.12.1

DIGITAL OFFSET ERROR

CALIBRATION

The

Offset

Calibration

(OFFSETCAL,

address: 0x9) is a signed MSb first, two’s complement

coding, 24-bit register that holds the digital offset

calibration value, OFFSETCAL. The OFFSETCAL

equivalent input voltage value is calculated with

Equation 5-7.

EQUATION 5-7:

OFFSETCAL

CALIBRATION VALUE

(EQUIVALENT INPUT

VOLTAGE)

For the MCP3461/2/4 devices, the offset calibration is

done by adding bit-by-bit the OFFSETCAL[23:8]

calibration value to the ADCDATA code. The last byte

of the OFFSETCAL register (OFFSETCAL[7:0]) is

ignored and internally reset to 0x00 during the

calibration, therefore the addition just takes into

account the OFFSETCAL[23:8] bits and is done

bit-by-bit with the ADC output code.

The offset calibration value range in equivalent voltage

is [-VREF/GAIN; (+VREF – 1 LSb)/GAIN], which permits

cancellation of any possible offset in the ADC, but also

in the system. The offset calibration is realized with a

simple 16-bit signed adder and is instantaneous (no

pipeline delay). Enabling the offset calibration will

affect the next conversion result; the conversion result

already held in the ADCDATA Output register (0x0) is

not modified when the EN_OFFCAL is set to ‘1’, but

the next one will take in account the offset calibration.

Changing the OFFSETCAL register to a new value will

not affect the current ADCDATA value, but the next

one (after a data ready interrupt) will take into account

the new OFFSETCAL value. Figure 5-11 shows the

different cases and their implication on the ADCDATA

ADCDATA (post-calibration) =

[ADCDATA (pre-calibration) + OFFSETCAL] x GAINCAL

OFFSETCAL (V) =

VREF * (OFFSETCAL[23:8])/(32768 * GAIN)

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