IMXRT1160CEC datasheet(80/124 Pages) NXP

80 / 124 page

i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021

NXP Semiconductors

Electrical characteristics

SR_LS

Slew rate in Low Speed

mode

Code 100h — F00h or

F00h — 100h @ZTC

current

—0.24

—

s

Code 100h — F00h or

F00h —100h @PTAT

current

—0.24

—

SR_MS

Slew rate in Middle

Speed mode

Code 100h — F00h or

F00h — 100h @ZTC

current

—1.2

—

Code 100h — F00h or

F00h —100h @PTAT

current

—1.2

—

SR_HS

Slew rate in High Speed

mode

Code 100h — F00h or

F00h — 100h @ZTC

current

—2.4

—

Code 100h — F00h or

F00h —100h @PTAT

current

—2.4

—

PSRR

Power supply rejection

ratio

Code 800h,

VDD_ANA18 = 100 mV,

VREFH_ANA12 selected

—70

—

Glitch

Glitch energy

Code 100h — F00h —

100h

—30

—

nV-s

—

Code 7FFh — 800h —

7FFh

—30

—

Channel to channel

crosstalk

—

-80

ROP

Output resistance

Code 100h — F00h and

Rload = 18 k



—200

—



1 It is recommended to operate the DAC in the output voltage range between 0.15 V and (VDDA_ADC_1P8 - 0.15 V) for best

accuracy. Linearity of the output voltage outside this range will be affected as current load increases.

2 When ADC_VREFH is selected as the reference (DAC_CR[DACRFS] = 0b).

3 When the internal 1.2 V source is selected as the reference (DAC_CR[DACRFS] = 1b).

4 The DAC output remains within ±0.5 LSB of the final measured value for digital input code change. Noise on the power supply

can cause this performance to degrade to ±1 LSB. This parameter represents both rising edge and falling edge settling time.

5 Time for the DAC output to transition from 10% to 90% signal amplitude (rising edge or falling edge).

6 PSRR = 20 x log{ΔVDD_ANA18 /ΔVDAC_OUT}

7 If two DACs are used and sharing the same VREFH.

8 Based on design simulation.

Table 77. DAC characteristics (continued)

Symbol

Description

Test Conditions

Min

Typ

Max

Unit

Notes

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