IMXRT1160CEC datasheet(30/124 Pages) NXP

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i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021

NXP Semiconductors

Electrical characteristics

Set Point #11

Active

• CM7 is power off; CM4 runs at 200 MHz, drive

voltage to 1.0 V

• CM4 domain bus frequency at 100 MHz

• DCDC is off, LDO_LPSR_ANA and

LDO_LPSR_DIG are active

• 16 MHz, 400 MHz, and external 32 kHz crystal are

enabled

• All PLLs are power gated

• The WAKEUPMIX domain, MEGAMIX domain,

and DISPLAYMIX domain are power gated

• All peripherals in LPSRMIX domain are clocked

DCDC_IN

26.5

A

VDD_LPSR_IN

37.2

43.2

VDD_SNVS_IN

3.9

8.9

A

Total

122.860

142.715

Set Point #12

Active

• CM7 is power off; CM4 runs at 100 MHz, lower

voltage to 0.9 V

• CM4 domain bus frequency at 50 MHz

• DCDC is off, LDO_LPSR_ANA and

LDO_LPSR_DIG are active

• 16 MHz, 400 MHz, and external 32 kHz crystal are

enabled

• All PLLs are power gated

• The WAKEUPMIX domain, MEGAMIX domain,

and DISPLAYMIX domain are power gated

• All peripherals in LPSRMIX domain are clocked

DCDC_IN

26.5

37.8

A

VDD_LPSR_IN

22.5

26.5

VDD_SNVS_IN

3.8

8.7

A

Total

74.350

87.603

Set Point #0

Standby

Suspend

• System is on STANDBY mode

• Both CM7 and CM4 are on SUSPEND mode

• TCM is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals clock gated, but remain powered

DCDC_IN

3.1

15.4

VDD_LPSR_IN

32.3

40.9

A

VDD_SNVS_IN

3.8

8.5

A

Total

10.349

50.983

Set Point #5

Standby

Suspend

• System is on STANDBY mode

• Both CM7 and CM4 are on SUSPEND mode

• TCM is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals are clock gated, but remain

powered

DCDC_IN

2.3

11.7

VDD_LPSR_IN

32.4

41.1

A

VDD_SNVS_IN

3.8

8.5

A

Total

7.709

38.774

Set Point #7

Standby

Suspend

• System is on STANDBY mode

• Both CM7 and CM4 are on SUSPEND mode

• TCM is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals are clock gated, but remain

powered

DCDC_IN

2.3

11.7

VDD_LPSR_IN

32.4

41.1

A

VDD_SNVS_IN

3.8

8.5

A

Total

7.709

38.774

Table 13. Typical power modes current and power consumption (Dual core) (continued)

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