IMXRT1160CEC datasheet(21/124 Pages) NXP

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i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021

NXP Semiconductors

3.2

Recommended connections for unused analog interfaces

Table 6 shows the recommended connections for unused analog interfaces.

JTAG_nnnn

External resistors can be used with all JTAG signals except for JTAG_TDO, but they are not

required. See Table 5 for a summary of the JTAG interface.

JTAG_TDO is configured with an on-chip keeper circuit, such that the floating condition is actively

eliminated if an external pull resistor is not present. An external pull resistor on JTAG_TDO is

detrimental. See Table 5 for a summary of the JTAG interface.

When JTAG_MOD is low, the JTAG interface is configured for a common software debug, adding

all the system TAPs to the chain.

When JTAG_MOD is high, the JTAG interface is configured to a mode compliant with the IEEE

1149.1 standard.

These signals are No Connect (NC) and should not be connected by the user.

POR_B

See the System Boot chapter in the reference manual for the correct boot configuration. Note that

an incorrect setting may result from an improper boot sequence.

POR_B signal has internal 100 k

 pull up to SNVS domain, should pull up to VDD_SNVS_ANA if

need to add external pull up resistor, otherwise it will cause additional leakage during SNVS mode.

It is recommended to add the external reset IC to the circuit to guarantee POR_B is properly

processed during power up/down, please refer to the EVK design for details.

Note:

• As the Low DCDC_IN detection threshold is 2.6 V, the reset IC’s reset threshold must be higher

than 2.6 V, then the whole chip is reset before the internal DCDC module reset to guarantee the

chip safety during power down.

• For power on reset, on any conditions ones need to make sure the voltage on DCDC_PSWITCH

pin is below 0.5 V before power up.

ONOFF

A brief connection to GND in the OFF mode causes the internal power management state machine

to change the state to ON. In the ON mode, a brief connection to GND generates an interrupt

(intended to be a software-controllable power-down). Approximately five seconds (or more) to GND

causes a forced OFF. Both boot mode inputs can be disconnected.

TEST_MODE

This input is reserved for NXP manufacturing use. The user must tie this pin directly to GND.

WAKEUP

A GPIO powered by SNVS domain power supply which can be configured as wakeup source in

SNVS mode.

Table 5. JTAG controller interface summary

JTAG

I/O Type

On-chip Termination

JTAG_TCK

Input

20–50 k



pull-down

JTAG_TMS

Input

20–50 k



pull-up

JTAG_TDI

Input

20–50 k



pull-up

JTAG_TDO

3-state output

High-impedance

JTAG_TRSTB

Input

20–50 k



pull-up

JTAG_MOD

Input

20–50 k



pull-down

Table 4. Special signal considerations (continued)

Signal Name

Remarks

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