IMXRT1160CEC datasheet(29/124 Pages) NXP

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Electrical characteristics

i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021

NXP Semiconductors

4.1.5

Typical power mode supply currents

Table 13 shows the current and power consumption (not including I/O) of i.MX RT1160 processors in

selected power modes.

Table 13. Typical power modes current and power consumption (Dual core)

Modes

Test conditions

Power supplies at 3.3 V (Typical)1

Units

25 oC Tj

95 oC Tj

Set Point #0

Active

• CM7 runs at 600 MHz, drive voltage to 1.0 V; CM4

runs at 240 MHz, drive voltage to 1.0 V

• CM7 domain bus frequency at 200 MHz; CM4

domain bus frequency at 120 MHz

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• 16 MHz, 400 MHz, external 24 MHz crystal, and

external 32 kHz crystal are enabled

• All PLLs are enabled

• All peripherals are enabled and run at their

maximum clock root frequency under normal drive

mode

DCDC_IN

87.8

135.6

VDD_LPSR_IN

28.2

29.5

A

VDD_SNVS_IN

3.9

9.6

A

Total

289.846

447.609

Set Point #5

Active

• CM7 runs at 240 MHz, lower voltage to 0.9 V;

CM4 runs at 120 MHz, lower voltage to 0.9 V

• CM7 domain bus frequency at 100 MHz; CM4

domain bus frequency at 60 MHz

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• 16 MHz, 400 MHz, external 24 MHz crystal, and

external 32 kHz crystal are enabled

• All PLLs are enabled

• All peripherals are enabled and run at their

maximum clock root frequency under underdrive

mode

DCDC_IN

43.7

69.1

VDD_LPSR_IN

28.1

29.4

A

VDD_SNVS_IN

3.9

A

Total

144.316

228.157

Set Point #7

Active

• CM7 runs at 200 MHz, lower voltage to 0.9 V;

CM4 is clock gated, lower voltage to 0.9 V

• CM7 domain bus frequency at 100 MHz

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• 16 MHz, 400 MHz, and external 32 kHz crystal are

enabled

• All PLLs are power gated

• All peripherals controlled by CM4 core are clock

gated, but remain powered

DCDC_IN

25.4

47.8

VDD_LPSR_IN

27.9

29.3

A

VDD_SNVS_IN

3.9

8.8

A

Total

83.925

157.866

Set Point #9

Active

• CM7 is clock gated, lower voltage to 0.9 V; CM4

runs at 100 MHz, lower voltage to 0.9 V

• CM4 domain bus frequency at 50 MHz

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• 16 MHz, 400 MHz, and external 32 kHz crystal are

enabled

• All PLLs are power gated

• All peripherals controlled by CM7 core are clock

gated, but remain powered

DCDC_IN

14.7

34.6

VDD_LPSR_IN

27.8

29.1

A

VDD_SNVS_IN

3.8

8.7

A

Total

48.614

114.305

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