DP8428 datasheet(12/26 Pages) NSC

12 / 26 page

DP8428DP8429 Mode Descriptions (Continued)

CASIN goes low to access a new memory location (see

Figure 5c ) Parameter tCPdif has been specified in order that

users may easily determine minimum CAS pulse widths

when CASIN is toggling

AUTOMATIC CAS GENERATION

CAS is held high when RC is high even if CASIN is low If

CASIN is low when RC goes low CAS goes low automati-

cally tASC after the column address is valid This feature

eliminates the need for an externally derived CASIN signal

to control CAS when performing a simple access (

Figure 5a

demonstrates Auto-CAS generation in mode 4) Page or nib-

ble accessing may be performed as shown in

Figure 5c

even if CAS is generated automatically for the initial access

FASTEST MEMORY ACCESS

The fastest Mode 4 access is achieved by using the auto-

matic CAS feature and external delay line to generate the

required delay between RASIN and RC The amount of

delay required depends on the minimum tRAH of the DRAMs

being used The DP8429 parameter tDIF1 has been speci-

fied in order that the delay between RASIN and RC may be

minimized

tDIF1 e MAXIMUM (tRPDL -tRHA)

where tRPDL e RASIN to RAS delay

and tRHA e row address held from RC going low

The delay between RASIN and RC that guarantees the

specified DRAM tRAH is given by

MINIMUM RASIN to RC e tDIF1 a tRAH

Example

In an application using DRAMs that require a minimum tRAH

of 15 ns the following demonstrates how the maximum

RASIN to CAS time is determined

With tDIF1 (from Switching Characteristics) e 7 ns

RASIN to RC delay e 7ns a 15 ns e 22 ns

A delay line of 25 ns will be sufficient

With Auto-CAS generation the maximum delay from RC to

CAS (loaded with 600 pF) is 46 ns Thus the maximum

RASIN to CAS time is 71 ns under the given conditions

With a maximum RASIN to RAS time (tRPDL) of 20 ns the

maximum RAS to CAS time is about 51 ns Most DRAMs

with a 15 ns minimum tRAH have a maximum tRCD of about

60 ns Thus memory accesses are likely to be RAS limited

instead of CAS limited In other words memory access time

is limited by DRAM performance not controller perform-

ance

REFRESHING IN CONJUNCTION WITH MODE 4

If using mode 4 to access memory mode 0 (externally con-

trolled refresh) must be used for all refreshing

MODE 5 – AUTOMATIC ACCESS WITH HIDDEN RE-

FRESHING CAPABILITY

Automatic-Access has two advantages over the externally

controlled access (mode 4) First RAS CAS and the row to

column change are all derived internally from one input sig-

nal RASIN Thus the need for an external delay line (see

mode 4) is eliminated

Secondly since RC and CASIN are not needed to gener-

ate the row to column change and CAS these pins can be

used for the automatic refreshing function

AUTOMATIC ACCESS CONTROL

Mode 5 of the DP8429 makes accessing Dynamic RAM

nearly as easy as accessing static RAM Once row and col-

umn addresses are valid (latched on the DP8429 if neces-

sary) RASIN going low is all that is required to perform the

memory access

TLF8649 – 19

FIGURE 5c Page or Nibble Access in Mode 4

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