banks of 22 DRAMs each or 88 DRAMs including trace capacitance

unless otherwise noted See

Figure 11 for test load Maximum propagation delays are specified with all outputs

switching

Preliminary

Symbol

Access Parameter

Condition

CL

Units

Min

Max

Min

Max

RAS to CAS Low Delay

Figure 6

34

63

ns

DP8428-8029-80

RAS to CAS Low Delay

Figure 6

34

55

ns

DP8428-7029-70

RAS to CAS High Delay

Figure 6

22

ns

Row Address Hold Time

Figure 6

25

25

ns

Row Address Hold Time

Figure 6

15

15

ns

Column Address Set-up Time

Figure 6

00

ns

(Mode 5)

RASIN to Column Address

Figure 6

94

ns

DP8428-8029-80

RASIN to Column Address

Figure 6

85

ns

DP8428-7029-70

RASIN to Column Address

Figure 6

76

ns

DP8428-8029-80

RASIN to Column Address

Figure 6

68

ns

DP8428-7029-70

RASIN to RAS Low Delay

Figures 5a 5b 6

21

18

ns

RASIN to RAS High Delay

Figures 5a 5b 6

20

17

ns

Address Set-up to RASIN low

Figures 5a 5b 6

13

ns

Address Input to Output

Figures 5a 5b 6

36

25

ns

Delay

Address Strobe High to

Figures 5a 5b

48

ns

Address Output Valid

Address Set-up Time to ADS

Figures 5a 5b 6

5ns

Address Hold Time from ADS

Figures 5a 5b 6

10

ns

Address Strobe Pulse Width

Figures 5a 5b 6

26

ns

WIN to WE Output Delay

Figure 5b

28

ns

CASIN to CAS Low Delay

Figure 5b

17

33

ns

(RC low Mode 4)

CASIN to CAS High Delay

Figure 5b

13

33

ns

(RC low Mode 4)

See Mode 4

13

ns

Description

Column Select to Column

Figure 5a

41

ns

Address Valid

Row Select to Row

Figures 5a 5b

45

ns

Address Valid

Row Address Held from

Figure 5a

7ns

Column Select

RC Low to CAS Low Delay

Figure 5a

50

ns

(CASIN Low Mode 4)

DP8428-8029-80

RC Low to CAS Low Delay

Figure 5a

46

ns

(CASIN Low Mode 4)

DP8428-7029-70

See Mode 4

7

ns

Description

ns

21