DP8428 datasheet(7/26 Pages) NSC

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DP8428DP8429 Mode Descriptions

MODE 0 – EXTERNALLY CONTROLLED REFRESH

Figure 2 shows the Externally Controlled Refresh timing In

this mode the refresh counter contents are multiplexed to

the address outputs All RAS outputs are enabled to follow

RASIN so that the row address indicated by the refresh

counter is refreshed in all DRAM banks when RASIN goes

low The refresh counter increments when RASIN goes

high RFSH should be held low at least until RASIN goes

high (they may go high simultaneously) so that the refresh

address remains valid and all RAS outputs remain enabled

throughout the refresh

A burst refresh may be performed by holding RFSH low and

toggling RASIN until all rows are refreshed It may be useful

in this case to reset the refresh counter just prior to begin-

ning the refresh The refresh counter resets to all zeroes

when RFIO is pulled low by an external gate The refresh

counter always counts to 511 before rolling over to zero If

there are 128 or 256 rows being refreshed then Q7 or Q8

respectively going high may be used as an end-of-burst

indicator

In order that the refresh address is valid on the address

outputs prior to the RAS lines going low RFSH must go low

before RASIN The setup time required is given by tRFLRL in

the Switching Characteristics This parameter may be ad-

justed using

Figure 10 for loading conditions other than

those specified

TABLE III DP8428DP8429 Mode Select Options

Mode

(RFSH)

Mode of Operation

Externally Controlled

Refresh

Auto Refresh – Forced

Externally Controlled

Access

Auto Access

(Hidden Refresh)

DP8428DP8429 Interface Between System and DRAM Banks

TLF8649 – 12

All 9 Bits of Refresh Counter Used

FIGURE 1a DP8428DP8429 with 256k DRAMs

TLF8649 – 25

All 9 Bits of Refresh Counter Used

FIGURE 1b DP8428DP8429 with 1M DRAMs

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