TLF8649

September 1991

DP8428NS32828 DP8429NS32829

1 Megabit High Speed Dynamic RAM ControllerDrivers

General Description

The DP8428 and DP8429 1M DRAM ControllerDrivers are

designed to provide ‘‘No-Waitstate’’ CPU interface to Dy-

namic RAM arrays of up to 8 Mbytes and larger The

DP8428 and DP8429 are tailored for 32-bit and 16-bit sys-

tem requirements respectively Both devices are fabricated

using National’s new oxide isolated Advanced Low power

Schottky (ALS) process and use design techniques which

enable them to significantly out-perform all other LSI or dis-

crete alternatives in speed level of integration and power

consumption

Each device integrates the following critical 1M DRAM con-

troller functions on a single monolithic device ultra precise

delay line 9 bit refresh counter fall-through row column

and bank select input latches RowColumn address mux-

ing logic on-board high capacitive-load RAS CAS Write

Enable and Address output drivers and precise control sig-

nal timing for all the above

In order to specify each device for ‘‘true’’ worst case operat-

ing conditions all timing parameters are guaranteed while

the chip is driving the capacitive load of 88 DRAMs includ-

ing trace capacitance The chip’s delay timing logic makes

use of a patented new delay line technique which keeps AC

DP8429 guarantee a maximum RASIN to CASOUT delay of

80 ns or 70 ns even while driving an 8 Mbyte memory array

with error correction check bits included Two speed select-

ed options of these devices are shown in the switching

characteristics section of this document

(Continued)

Features

Y

Makes DRAM interface and refresh tasks appear virtu-

ally transparent to the CPU making DRAMs as easy to

use as static RAMs

Y

Specifically designed to eliminate CPU wait states up to

10 MHz or beyond

Y

Eliminates 20 discrete components for significant board

real estate reduction system power savings and the

elimination of chip-to-chip AC skewing

Y

On-board ultra precise delay line

Y

On-board high capacitive RAS CAS WE and Address

drivers (specified driving 88 DRAMs directly)

Y

AC specified for directly addressing up to 8 Mbytes

Y

Low powerhigh speed bipolar oxide isolated process

Y

Downward pin and function compatible with 256k

DRAM ControllerDrivers DP8409A DP8417 DP8418

and DP8419

Contents

Y

System and Device Block Diagrams

Y

Recommended Companion Components

Y

Device Connection Diagrams and Pin Definitions

Y

Device DifferencesDP8428 vs DP8429

Y

Mode of Operation

(Descriptions and Timing Diagrams)

Y

Application Description and Diagrams

Y

DCAC Electrical Specifications Timing Diagrams and

Test Conditions

System Diagram

TLF8649 – 1

TRI-STATE

is a registered trademark of National Semiconductor Corp

PAL

is a registered trademark of and used under license with Monolithic Memories Inc

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A