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ADL5580BCCZ-R7 датащи(PDF) 16 Page - Analog Devices

номер детали ADL5580BCCZ-R7
подробное описание детали  Fully Differential, 10 GHz ADC Driver with 10 dB Gain
PDF  22 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADL5580BCCZ-R7 датащи(HTML) 16 Page - Analog Devices

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ADL5580
Data Sheet
Rev. 0 | Page 16 of 22
APPLICATIONS INFORMATION
Figure 32 shows the basic connection diagram, and Table 8
describes the operation of the ADL5580.
The ADL5580 is sensitive to power supplies. Power rail voltages
must be brought up and applied in a monotonically increasing
manner without any glitches to avoid issues with the internal
digital logic.
The ADL5580 can be ac-coupled, as shown in Figure 32, or the
device can be dc-coupled if within the specified input and
output VCM ranges.
BASIC CONNECTIONS
BALANCED
AC
BALANCED
LOAD
ADL5580
RL
+
0.1µF
0.1µF
½ RS
2
½ RS
0.1µF
0.1µF
0.1µF
VINP
VINN
VOUTP
CS
VOUTN
EN
GND
+5V
–1.8V
1, 3, 5, 6, 10, 11, 13, 15, 16, 20
0.1µF
0.1µF
VCMI
0.1µF
0.1µF
4
19
18
PAD1
PAVCC
PAVCC
MAVEE
MAVEE
14
12
VCMO
17
7
SCLK
8
SDIO
9
PAD4
PAD3
PAD2
Figure 32. Basic Connection Diagram
Table 8. Basic Connections of the ADL5580
Functional Blocks
Pin No.
Mnemonic Description
Basic Connection
5 V
PAD1, PAD4
PAVCC
Amplifier analog supply
voltage, 5 V
Decouple each PAVCC pad via 100 pF, 1 µF capacitors
to ground. Ensure that the decoupling capacitors are
located close to the pads.
−1.8 V
PAD2, PAD3
MAVEE
Amplifier analog supply
voltage, −1.8 V
Decouple each MAVEE pad via 100 pF, 1 µF capacitors
to ground. Ensure that the decoupling capacitors are
located close to the pads.
RF Input
Differential RF inputs
Connect these pins to a differential configuration.
2
VINP
Positive RF Input
4
VINN
Negative RF Input
18
VCMI
VCM for the RF input signal
RF Output
Differential RF outputs
Connect the RF outputs to a power meter, network
analyzer, noise figure meter, or spectrum analyzer.
12
VOUTN
Negative RF output
14
VOUTP
Positive RF output
17
VCMO
VCM for the RF output signal
Serial Port
7
CS
Chip select active low
1.8 V to 3.3 V tolerant logic levels.
8
SCLK
SPI clock
1.8 V to 3.3 V tolerant logic levels.
9
SDIO
SPI data input output
1.8 V to 3.3 V tolerant logic levels.
AMP Control
19
EN
Amplifier enable
1.8 V to 3.3 V tolerant logic levels.
Ground
1, 3, 5, 6, 10, 11,
13, 15, 16, 20
GND
Ground
Connect the GND pins to the ground of the PCB.



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