ADL5580BCCZ-R7 datasheet(15/22 Pages) AD

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Data Sheet

ADL5580

Rev. 0 | Page 15 of 22

THEORY OF OPERATION

The ADL5580 is a fixed voltage gain (10 dB), fully differential,

high linearity amplifier, and ADC driver that operates on a dual

power supply voltage, +5 V and −1.8 V.

The small signal −3 dB bandwidth is 10.0 GHz, and all of the

integrated building blocks of the ADL5580 are programmable via

the SPI.

RF INPUT AND OUTPUT WITH COMMON-MODE

NETWORK

The input impedance is 100 Ω differential, and the output

impedance is 50 Ω differential, which allows users to drive

ADCs like the AD9213 directly without any matching networks,

that is at a 50 Ω differential input. For load conditions other

than 50 Ω differential, external termination networks are

required.

The input and output termination blocks have four operation

modes that allow users to set the input and output common-

mode operation through Register 0x100, Bits[7:0], see Table 7.

In Mode 00, the VCM terminal must be provided externally on

the input termination and the output termination blocks.

For Mode 01, the internal voltage generator (the voltage controlled

by two bits) is activated, and the VCM terminal input and output

termination blocks are driven to the internal reference voltage.

If the internal reference voltage and the connecting termination

blocks have a different VCM, the behavior of the system is

undefined and must be avoided.

Mode 10 is identical to Mode 01 except that the VCMO and

VCMI pins are driven to the internal reference voltage to

convey the internal VCM to the connecting termination blocks.

Use Mode 11 to set the internal VCM termination to externally

provide the voltage for the VCMx pins.

RF SIGNAL CHAIN

The ADL5580 provides another level of control to optimize

flatness or wider bandwidth. In applications where flatness is

critical, the ADL5580 offers flatness optimization at the

expense of the operating bandwidth. However, if the operating

bandwidth is critical, the ADL5580 offers tuning options

through the peaking control bits, PRG_CPEAK_1P8V

(Register 0x101, Bits[6:4]).

Enable

The enable bits (EN_AMP_1P8V and EN_REF_1P8V) are

located in Register 0x101, Bit 1 and Bit 0, respectively. These

particular enable bits control enabling the amplifier (EN_

AMP_1P8V) and the reference (EN_REF_1P8V). The ADL5580

can be enabled or disabled by using the EN pin (Pin 19), a real-

time external pin with no SPI latency

PROGRAMMABILITY GUIDE

Viewing the register map at the highest level, the registers are

subdivided into three memory map functional blocks (see Table 6).

See Table 9 for a complete list of all the registers on the

ADL5580.

Table 6. Memory Map Functional Blocks

Functional Blocks

0x000 to 0x011

Analog Devices SPI configuration

0x100 to 0x101, 0x200

Signal path configuration, enable

0x300

Optional linearity optimization

SPI

The SPI of the ADL5580 allows the user to configure the device

for specific functions or operations via a 3-wire SPI port. It

includes enable blocks, the bias current level, transfer function

peaking, change input and output termination block operation

modes, and change input and output VCM termination for

certain operation modes. This SPI provides users with added

flexibility and customization and consists of three control lines:

SCLK, SDIO, and CS. The timing requirements for the SPI port

are shown in Table 2.

The ADL5580 input logic level for the write cycle is with a 1.8 V

logic level.

On a read cycle, the SDIO is configurable for 1.8 V (default) or

3.3 V output levels by setting the SPI_1P8_3P3_CTRL bit

(Register 0x200, Bit 0).

Table 7. Common-Mode Setup Modes

Mode

Output VCM (V)

Output Internal VCM

VCMO Pin

Input VCM (V)

Input Internal VCM

VCMI Pin

0.41

Disabled

Disconnect

1.39

Disabled

Disconnect

0.51

Enabled

Disconnect

1.53

Enabled

Disconnect

0.60

Enabled

Export

1.67

Enabled

Export

0.70

Disabled

Import

1.80

Disabled

Import

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