ADL5580

Data Sheet

Rev. 0 | Page 6 of 22

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Output Voltage

SDIO

At 1.8 V

Register 0x200, Bit 0 = 0x0

−1 mA static load

1.5

V

0.2

V

At 3.3 V

Register 0x200, Bit 0 = 0x1

2.7

V

0.2

V

SUPPLY AND POWER SPECIFICATIONS

Power

1.76

W

Shutdown Power

At room temperature

11

mW

Shutdown Current

At room temperature

2

mA

Positive Supply

5%

4.75

5.0

5.25

V

276

mA

Negative Supply

5%

−1.7

−1.8

−1.89 V

−224

mA

1

S parameters are taken with the device under test (DUT) itself. The printed circuit board (PCB) is not used in the measurement.

2

NSD (RTI) = ½ ×

/10

4 × (10

1) ×

NF

IN

kT

R

−

where:

T is the standard absolute temperature for evaluating noise figure, which equals 290 K.

DIGITAL LOGIC TIMING

Table 2.

Parameter

Description

Min

Typ

Max

Unit

25

MHz

Minimum period that SCLK is in logic high state

10

ns

Minimum period that SCLK is in logic low state

10

ns

Setup time between data and rising edge of SCLK

5

ns

Hold time between data and rising edge of SCLK

5

ns

Setup time between falling edge of CS and rising edge of SCLK

10

ns

Hold time between rising edge of CS and the last falling edge of SCLK

10

ns

Maximum time delay between falling edge of SCLK and output data valid for a read operation

5

14

ns

tz

Maximum time delay between CS deactivation and SDIO bus return to high impedance

12

ns

Timing Diagrams

R/W

A3

A2

A1

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

A7

A6

A5

A4

A8

A13 A12

A14

ADDRESS

A11 A10 A9

SCLK

CS

SDI

Figure 2. Serial Port Interface Register Timing, MSB First