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TMS320F28076PZP датащи(PDF) 46 Page - Texas Instruments |
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TMS320F28076PZP датащи(HTML) 46 Page - Texas Instruments |
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46 / 192 page ![]() 7.9.2.2.2 Reset ( XRS) Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tw(RSL1) Pulse duration, XRS driven low by device after supplies are stable 100 µs tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles th(boot-mode)(B) XRS (A) Boot-Mode Pins V V (3.3 V) DDIO DDA , V (1.2 V) DD User-code dependent Boot-ROM execution starts Peripheral/GPIO function Based on boot code GPIO pins as input CPU Execution Phase Boot ROM User-code I/O Pins GPIO pins as input (pullups are disabled) User-code dependent tw(RSL1) A. The XRS pin can be driven externally by a supervisor or an external pullup resistor, see Section 6.2.1. B. After reset from any source (see Section 7.9.2.1), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled. Figure 7-5. Power-on Reset th(boot-mode)(A) XRS Boot-Mode Pins I/O Pins CPU Execution Phase Boot-ROM execution starts (initiated by any reset source) User-Code Execution Starts User Code Boot ROM User-Code Dependent User Code Peripheral/GPIO Function User-Code Dependent GPIO Pins as Input (Pullups are Disabled) GPIO Pins as Input Peripheral/GPIO Function tw(RSL2) A. After reset from any source (see Section 7.9.2.1), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled. Figure 7-6. Warm Reset TMS320F28076, TMS320F28075 SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021 www.ti.com 46 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28076 TMS320F28075 |
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