TMS320F28076PZP datasheet(3/192 Pages) TI

3 / 192 page

Connectivity peripherals such as dual Controller Area Network (CAN) modules (ISO 11898-1/CAN 2.0B-

compliant) and a USB 2.0 port with MAC and full-speed PHY let users add universal serial bus (USB)

connectivity to their application.

To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.

Device Information

PART NUMBER(1)

PACKAGE

BODY SIZE

TMS320F28076PTP

HLQFP (176)

24.0 mm × 24.0 mm

TMS320F28075PTP

HLQFP (176)

24.0 mm × 24.0 mm

TMS320F28076PZP

HTQFP (100)

14.0 mm × 14.0 mm

TMS320F28075PZP

HTQFP (100)

14.0 mm × 14.0 mm

(1)

For more information, see Mechanical, Packaging, and Orderable Information.

Functional Block Diagram

Figure 4-1 shows the CPU system and associated peripherals.

12-bit ADC

ADC

Result

Regs

Peripheral Frame 1

GPIO MUX, Input X-BAR, Output X-BAR

Secure Memories

shown in Red

CPU1 Buses

Comparator

Subsystem

(CMPSS)

DAC

Config

Data Bus

Bridge

ePWM-1/../12

eCAP-

1/../6

eQEP-1/2/3

HRPWM-1/../8

SDFM-1/2

SCI-

A/B/C/D

(16L FIFO)

I2C-A/B

(16L FIFO)

Data Bus Bridge

CAN-

A/B

(32-MBOX)

Data Bus

Bridge

Peripheral Frame 2

SPI-

A/B/C

(16L FIFO)

McBSP-A/B

GPIO

Data Bus

Bridge

Data Bus

Bridge

USB

Ctrl /

PHY

EMIF1

Data Bus

Bridge

JTAG

AUXCLKIN

External Crystal or

Oscillator

Watchdog

Main PLL

Aux PLL

INTOSC1

INTOSC2

Low-Power

Mode Control

GPIO MUX

TRST

TCK

TDI

TMS

TDO

MEMCPU1

Global Shared

8x 4Kx16

GS0-GS7 RAMs

C28 CPU-1

FPU

TMU

CPU Timer 0

CPU Timer 1

CPU Timer 2

ePIE

(up to 192

interrupts)

WD Timer

NMI-WDT

CPU1.CLA1 Data ROM

(4Kx16)

CPU1.CLA1 to CPU1

128x16 MSG RAM

CPU1 to CPU1.CLA1

128x16 MSG RAM

Boot-ROM 32Kx16

Nonsecure

Secure-ROM 32Kx16

Secure

CPU1.M0 RAM 1Kx16

CPU1.M1 RAM 1Kx16

CPU1.D0 RAM 2Kx16

CPU1.D1 RAM 2Kx16

CPU1 Local Shared

6x 2Kx16

LS0-LS5 RAMs

CPU1.CLA1

CPU1.DMA

PSWD

Dual

Code

Security

Module

Emulation

Code

Security

Logic

(ECSL)

PUMP

OTP/Flash

Wrapper

FLASH

256K x 16

Secure

User

Configurable

DCSM

OTP

1K x 16

A5:0

B3:0

D4:0

ADCIN14

ADCIN15

Analog

MUX

Figure 4-1. Functional Block Diagram

www.ti.com

TMS320F28076, TMS320F28075

SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021

Submit Document Feedback

Product Folder Links: TMS320F28076 TMS320F28075

TMS320F28076PZP датащи(PDF) 3 Page - Texas Instruments

TMS320F28076PZP датащи(HTML) 3 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL