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STPMIC1APQR датащи(PDF) 110 Page - STMicroelectronics

номер детали STPMIC1APQR
подробное описание детали  Highly integrated power management IC for micro processor units
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STPMIC1APQR датащи(HTML) 110 Page - STMicroelectronics

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6.5.12
Interrupt source register 2 (INT_SRC_R2)
Table 59. INT_SRC_R2
7
6
5
4
3
2
1
0
BST_OVP BST_OCP
SWOUT_OCP
VBUSOTG_OCP
BUCK4_OCP
BUCK3_OCP
BUCK2_OCP
BUCK1_OCP
R
R
R
R
R
R
R
R
Address: 0xB1
Type: read register
Default: 0x00
Description: interrupt source register 2. Register is set to default on RSTn assertion. State bit is 1 as long as
event source is active.
[7]
BST_OVP: overvoltage detection on Boost output
0: inactive
1: active
[6]
BST_OCP: Current limitation detection on Boost output
0: inactive
1: active
[5]
SWOUT_OCP: Current limitation detection on SWOUT
0: inactive
1: active
[4]
VBUSOTG_OCP: Current limitation detection on VBUSOTG
0: inactive
1: active
[3]
BUCK4_OCP: Current limitation detection on Buck4
0: inactive
1: active
[2]
BUCK3_OCP: Current limitation detection on Buck3
0: inactive
1: active
[1]
BUCK2_OCP: Current limitation detection on Buck2
0: inactive
1: active
[0]
BUCK1_OCP: Current limitation detection on Buck1
0: inactive
1: active
STPMIC1
Interrupt registers
DS12792 - Rev 7
page 110/140



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