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STPMIC1APQR датащи(PDF) 109 Page - STMicroelectronics

номер детали STPMIC1APQR
подробное описание детали  Highly integrated power management IC for micro processor units
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STPMIC1APQR датащи(HTML) 109 Page - STMicroelectronics

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6.5.11
Interrupt source register 1 (INT_SRC_R1)
Table 58. INT_SRC_R1
7
6
5
4
3
2
1
0
SWOUT
reserved
VBUSOTG
reserved
WKP
reserved
PKEY
reserved
R
R
R
R
R
R
R
R
Address: 0xB0
Type: read register
Default: 0x00
Description: interrupt source register 1. Register is reset on RSTn assertion.
State bit is 1 as long as event source is active.
[7]
SWOUT: SWOUT event source state
0: inactive
1: active
[6]
reserved
[5]
VBUSOTG: VBUSOTG event source state
0: inactive
1: active
[4]
reserved
[3]
WKP: WAKEUP event source state
0: inactive
1: active
[2]
reserved
[1]
PKEY: PONKEYn event source state
0: inactive
1: active
[0]
reserved
STPMIC1
Interrupt registers
DS12792 - Rev 7
page 109/140



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