STM32WL55JC datasheet(24/145 Pages) STMICROELECTRONICS

24 / 145 page

Functional overview

STM32WL55/54xx

24/145

DS13293 Rev 1

VDDRF1V5 pin and must be connected externally to VFBSMPS.

•

VBAT = 1.55 V to 3.6 V

VBAT is the power supply for RTC, TAMP, external clock 32 kHz oscillator and backup

registers (through power switch) when VDD is not present.

•

VREF-, VREF+

VREF+ is the input reference voltage for ADC and DAC. It is also the output of the

internal voltage reference buffer when enabled.

–

When VDDA < 2 V, VREF+ must be equal to VDDA.

–

When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA.

VREF+ can be grounded when ADC/DAC is not active. The internal voltage reference

buffer supports the following output voltages, configured with VRS bit in the

VREFBUF_CSR register:

–VREF+ around 2.048 V: this requires VDDA ≥ 2.4 V.

–VREF+ around 2.5 V: this requires VDDA ≥ 2.8 V.

During power up and power down, the following power sequence is required:

When VDD < 1 V other power supplies (VDDA) must remain below VDD + 300 mV.

During power down, VDD can temporarily become lower then other supplies only if the

energy provided to the device remains below 1 mJ. This allows external decoupling

capacitors to be discharged with different time constants during this transient phase.

When VDD > 1 V, all other power supplies (VDDA) become independent.

An embedded linear voltage regulator is used to supply the internal digital power VCORE.

VCORE is the power supply for digital peripherals, SRAM1 and SRAM2. The Flash memory

is supplied by VCORE and VDD. VCORE is split in two parts: VDDO part and an interruptible

part VDDI.

Figure 5. Power-up/power-down sequence

Note:

VDD, VDDRF and VDDSMPS must be wired together, so they can follow the same voltage

sequence.

MSv68044V1

0.3

VBOR0

3.6

Operating mode

Power-on

Power-down

time

VDDA

VDD

Invalid supply area

VDDA < VDD + 300 mV

VDDA independent from VDD

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