STM32WL55JC datasheet(46/145 Pages) STMICROELECTRONICS

46 / 145 page

Functional overview

STM32WL55/54xx

46/145

DS13293 Rev 1

–

programmable setup and hold times

–

clock stretching (optional)

•

SMBus (system management bus) specification rev 2.0 compatibility:

–

hardware PEC (packet error checking) generation and verification with ACK

control

–

address resolution protocol (ARP) support

–

SMBus alert

•

PMBus (power system management protocol) specification rev 1.1 compatibility

•

independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent from the PCLK reprogramming (see Figure 8)

•

wakeup from Stop mode on address match

•

programmable analog and digital noise filters

•

1-byte buffer with DMA capability

3.30

Universal synchronous/asynchronous receiver transmitter

(USART/UART)

The devices embed two universal synchronous receiver transmitters, USART1 and

USART2 (see Table 16 for the implementation details).

Each USART provides asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode. Each

USART has LIN Master/Slave capability and provides hardware management of the CTS

and RTS signals, and RS485 driver enable.

The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides

Smart Card mode (ISO 7816 compliant) and SPI-like communication capability.

The USART supports synchronous operation (SPI mode), and can be used as an SPI

master.

Table 15. I2C implementation

I2C features(1)

1. X = supported.

I2C1(2)

2. The register content is lost in Stop 2 mode.

I2C2(2)

I2C3

7-bit addressing mode

10-bit addressing mode

Standard-mode (up to 100 Kbit/s)

Fast-mode (up to 400 Kbit/s)

Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)

Independent clock

Wakeup from Stop mode

X(3)

3. Wakeup supported from Stop 0 and Stop 1 modes.

X(3)

X(4)

4. Wakeup supported from Stop 0, Stop 1 and Stop 2 modes.

SMBus/PMBus

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