STM32WL55JC datasheet(65/145 Pages) STMICROELECTRONICS

номер детали	STM32WL55JC

подробное описание детали	Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0 LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM

PDF	145 Pages

Scroll/Zoom	100%

производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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65 / 145 page

DS13293 Rev 1

65/145

STM32WL55/54xx

Electrical characteristics

135

5.3

Operating conditions

5.3.1

Main performances

5.3.2

General operating conditions

Table 24. Main performances at VDD = 3 V

Parameter

Test conditions

Typ

Unit

ICORE Core current consumption

VBAT (VBAT = 3V, VDD = 0 V)

0.005

µA

Shutdown

0.031

Standby (32-Kbyte RAM retention)

0.360

Stop 2, RTC enabled

Sleep (16 MHz)

770

LPRun (2 MHz)

220

Run, SMPS ON (48 MHz)

3450

Rx boosted

LoRa 125 kHz, SMPS ON

4.82

Tx low power

434 to 490 MHz, 14 dBm, 3.3 V

868 to 915 MHz, 14 dBm, 3.3 V

Tx high power

434 to 490 MHz, 22 dBm, 3.3 V

120

868 to 915 MHz, 22 dBm, 3.3 V

107

Table 25. General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

fHCLK

Internal AHB clock frequency

MHz

fPCLK1 Internal APB1 clock frequency

fPCLK2

Internal APB2 clock frequency

VDD

Standard operating voltage

1.8(1)

3.6

VDDA

Analog supply voltage

ADC or COMP used

1.62

3.6

DAC used

1.71

VREFBUF used

2.4

ADC, DAC, COMP and

VREFBUF not used

VBAT

Backup operating voltage

1.55

3.6

VFBSMPS SMPS feedback voltage

1.4

3.6

VDDRF Minimum RF voltage

1.8

3.6

VIN

I/O input voltage

TT I/O

–0.3

VDD + 0.3

All I/O except TT

–0.3

min between

min (VDD, VDDA) + 3.6 V

and 5.5 V(2)(3)

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