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STM32WL55JC датащи(PDF) 133 Page - STMicroelectronics

номер детали STM32WL55JC
подробное описание детали  Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0 LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
PDF  145 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WL55JC датащи(HTML) 133 Page - STMicroelectronics

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DS13293 Rev 1
133/145
STM32WL55/54xx
Electrical characteristics
135
Figure 27. SPI timing diagram - Slave mode and CPHA = 0
tv(SO)
Data output valid time
Slave mode, 2.7 < VDD < 3.6 V
Range 1
-
10
13.5
ns
Slave mode, 2.7 < VDD < 3.6 V
Range 2
-17
18
Slave mode, 1.8 < VDD < 3.6 V
Range 1
-10
20
Slave mode, 1.8 < VDD < 3.6 V
Range 2
-17
24
tv(MO)
Master mode (after enable edge)
-
1
1.5
th(SO)
Data output hold time
Slave mode (after enable edge)
8
-
-
th(MO)
Master mode (after enable edge)
0
-
-
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), that has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.
Table 95. SPI characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(SI)
MSB IN
BIT1 IN
LSB IN
BIT6 OUT
MSB OUT
LSB OUT
NSS input
MOSI
INPUT
MISO
OUTPUT
(SI)



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