STM32WL55JC datasheet(128/145 Pages) STMICROELECTRONICS

128 / 145 page

Electrical characteristics

STM32WL55/54xx

128/145

DS13293 Rev 1

5.3.24

Comparator characteristics

ENOB

Effective number of

bits

DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ,

1 kHz

-11.4

bits

DAC output buffer OFF, CL ≤ 50 pF, no RL,

1 kHz

-11.5

1. Guaranteed by design.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095.

4. Difference between the value measured at code (0x001) and the ideal value.

5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF

when buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.

Table 88. DAC accuracy(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 89. COMP characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Analog supply voltage

1.62

3.6

VIN

Comparator

input voltage range

-0

VDDA

VBG(2)

Scaler input voltage

VREFINT

VSC

Scaler offset voltage

±5

±10

IDDA(SCALER)

Scaler static consumption

from VDDA

BRG_EN = 0 (bridge disabled)

200

300

BRG_EN = 1 (bridge enabled)

0.8

µA

tSTART_SCALER Scaler startup time

100

200

µs

tSTART

Comparator startup time

to reach propagation

delay specification

High-speed

mode

VDDA ≥ 2.7 V

µs

VDDA < 2.7 V

Medium mode

VDDA ≥ 2.7 V

VDDA < 2.7 V

Ultra-low-power mode

tD(3)

Propagation delay with

100 mV overdrive

High-speed

mode

VDDA ≥ 2.7 V

VDDA < 2.7 V

100

Medium mode

0.55

0.9

µs

Ultra-low-power mode

Voffset

Comparator offset error

Full common mode range

±5

±20

Vhys

Comparator hysteresis

No hysteresis

Low hysteresis

Medium hysteresis

High hysteresis

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