ESD

PMU

VDD

Current

Main-

Modulator

Comparator

Bandgap-

Biasing

async logic

hys.-ctrl

GMR1

GMR3

Pre-Amplifier

Left

Right

LP-

+/-

Filter

Tracking-

ADC

GMR4

GMR2

GND

Left

Right

Offset-DAC

Oscillator

Fuses

dB

14mA

dB_limit

7mA

dB_limit

TLE5041plusC

Functional Description

2.4

Block Diagram

The device is supplied internally by a voltage regulator within the PMU. An on chip oscillator serves as clock

generator for the digital part of the circuit.

The TLE5041plusC incorporates two GMR sensing elements spaced at 2mm. The signal path is comprised of a

differential amplifier, a noise limiting low pass filter and two comparators. An offset cancellation loop is in place to

compensate magnetic and electric offsets. The regulation loop consists of a tracking A/D converter, the digital core

to evaluate the offset and the offset DAC to feed in the corrective voltage.

The current interface is triggered by the main comparator.

Figure 3

TLE5041plusC block diagram

The device can be in one of two operating modes, namely uncalibrated mode or calibrated mode. The term

calibration is related to the offset correction algorithm. The device starts up in uncalibrated mode. Most

performance parameters will not be guaranteed in this mode. While the magnet moves, the device observes the

magnetic input and adjusts for signal offsets. After a few periods the offset is calibrated and the device operates

with its full performance.

To prevent unwanted switching, the changes below a certain value dB

Figure 4

Differential amplitude and threshold dB

limit

Data Sheet

10

V 1.2, 2018-01-18