LSM6DSR datasheet(161/168 Pages) STMICROELECTRONICS

161 / 168 page

Table 106. EMB_FUNC_STATUS_MAINPAGE register ................................................ 69

Table 107. EMB_FUNC_STATUS_MAINPAGE register description ........................................ 69

Table 108. FSM_STATUS_A_MAINPAGE register .................................................... 70

Table 109. FSM_STATUS_A_MAINPAGE register description ............................................ 70

Table 110. FSM_STATUS_B_MAINPAGE register .................................................... 70

Table 111. FSM_STATUS_B_MAINPAGE register description ............................................ 70

Table 112. STATUS_MASTER_MAINPAGE register................................................... 71

Table 113. STATUS_MASTER_MAINPAGE register description .......................................... 71

Table 114. FIFO_STATUS1 register .............................................................. 72

Table 115. FIFO_STATUS1 register description ...................................................... 72

Table 116. FIFO_STATUS2 register .............................................................. 72

Table 117. FIFO_STATUS2 register description ...................................................... 72

Table 118. TIMESTAMP3 register ............................................................... 73

Table 119. TIMESTAMP2 register ............................................................... 73

Table 120. TIMESTAMP1 register ............................................................... 73

Table 121. TIMESTAMP0 register ............................................................... 73

Table 122. TAP_CFG0 register ................................................................. 74

Table 123. TAP_CFG0 register description ......................................................... 74

Table 124. TAP_CFG1 register ................................................................. 75

Table 125. TAP_CFG1 register description ......................................................... 75

Table 126. TAP priority decoding ................................................................ 75

Table 127. TAP_CFG2 register ................................................................. 75

Table 128. TAP_CFG2 register description ......................................................... 75

Table 129. TAP_THS_6D register ............................................................... 76

Table 130. TAP_THS_6D register description ....................................................... 76

Table 131. INT_DUR2 register.................................................................. 76

Table 132. INT_DUR2 register description ......................................................... 76

Table 133. WAKE_UP_THS register.............................................................. 77

Table 134. WAKE_UP_THS register description ..................................................... 77

Table 135. WAKE_UP_DUR register ............................................................. 77

Table 136. WAKE_UP_DUR register description ..................................................... 77

Table 137. FREE_FALL register ................................................................ 78

Table 138. FREE_FALL register description ........................................................ 78

Table 139. MD1_CFG register .................................................................. 79

Table 140. MD1_CFG register description.......................................................... 79

Table 141. MD2_CFG register .................................................................. 80

Table 142. MD2_CFG register description.......................................................... 80

Table 143. S4S_ST_CMD_CODE register ......................................................... 81

Table 144. S4S_ST_CMD_CODE register description ................................................. 81

Table 145. S4S_DT_REG register ............................................................... 81

Table 146. S4S_DT_REG register description ....................................................... 81

Table 147. I3C_BUS_AVB register ............................................................... 81

Table 148. I3C_BUS_AVB register description....................................................... 81

Table 149. INTERNAL_FREQ_FINE register........................................................ 82

Table 150. INTERNAL_FREQ_FINE register description................................................ 82

Table 151. INT_OIS register ................................................................... 83

Table 152. INT_OIS register description ........................................................... 83

Table 153. CTRL1_OIS register................................................................. 84

Table 154. CTRL1_OIS register description......................................................... 84

Table 155. DEN mode selection................................................................. 84

Table 156. CTRL2_OIS register................................................................. 85

Table 157. CTRL2_OIS register description......................................................... 85

Table 158. Gyroscope OIS chain digital LPF1 filter bandwidth selection ..................................... 85

Table 159. CTRL3_OIS register................................................................. 86

LSM6DSR

List of tables

DS11976 - Rev 2

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