MAS3506D datasheet(34/52 Pages) MICRONAS

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MAS 3506D

PRELIMINARY DATA SHEET

Micronas

PI13

BC-FRAME-SYNC

OUT

The BC-FRAME-SYNC is reset after POR and set to

‘1’ after each correctly decoded SCH. It will only be

cleared if the controller reads out SCH information

from the MAS 3506D.

PI12

BC-SYNC

OUT

The BC-SYNC is set, if the MAS 3506D is in the state

of proper decoding of the Broadcast Channel bit-

stream.

PI8

DECODING-ERROR

OUT

The Decoding-Error pin is activated, if during decoding

of the Broadcast Channel, the MPEG frame an error

occurs or if no input bitstream is applied.

PI4

MPEG-FRAME-SYNC

The MPEG-FRAME-SYNC signal indicates that an

MPEG header has been decoded properly and the

internal MPEG decoder is in a synchronized state. The

MPEG-FRAME-SYNC signal is inactive after Power-

On Reset and will be activated when a valid MPEG

Layer 3 header has been recognized. The signal will

be cleared if the ancillary data information is read out

by the controller via I2C interface.

PI3

AUD-SW

The AUD-SW input may sense the headphone jack

and deposit its information in Bit 3 of register c8hex

(please refer to Table 3–10 on page 20.) This way the

controller can get the information weather a loud-

speaker or a headphone should be supplied and can

set the BAS_INVR bit in DRD 3515A’s register

GLB_CONFIG accordingly.

PI2

RESERVED

PI1

RESERVED

PI0

RESERVED

4.3.6. Voltage Supervision And Other Functions

CLKI

CLKO

OUT

CLKI and CLKO are the input and output clock lines to

be connected to the DRD 3515A. CLKI expects

14.725 MHz, CLKO delivers 24.576 MHz synchronous

to the audio data stream.

PUP

POWER UP

OUT

The PUP output indicates that the power supply volt-

age exceeds its minimal level (software adjustable).

WSEN

DSP ENABLE

WSEN enables DSP and DC/DC-converter operation.

It must also be set to activate the control interface e.g.

to reprogram the DC/DC-converter.

WRDY

OUT

WRDY has two functionalities depending on the state

of the WSEN signal.

If WSEN = 0, it indicates that a valid clock has been

recognized at the CLKI clock input.

If WSEN = 1, the WRDY output will be set to ‘0’ until

the internal clock synthesizer has locked to the incom-

ing audio data stream, and thus, the CLKO clock out-

put signal is valid.

4.3.7. Serial Input Interface

SID

SII

SIC

Data, Frame Indication and Clock line of the serial

input interface. The SII line should be connected with

VSS in the standard WorldSpace mode. The SID and

SIC lines are used for the Broadcast Channel input.

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