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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ISM303DAC датащи(PDF) 54 Page - STMicroelectronics |
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ISM303DAC датащи(HTML) 54 Page - STMicroelectronics |
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54 / 80 page  Register description ISM303DAC 54/80 DocID030988 Rev 2 8 Register description 8.1 Module_8bit_A (0Ch) Module out value (r). This register is a read-only register. Table 30. Module_8bit_A register description 8.2 WHO_AM_I_A (0Fh) Who_AM_I register (r). This register is a read-only register. Its value is fixed at 43h. 8.3 CTRL1_A (20h) Control register 1 (r/w) Table 32. CTRL1_A register Table 33. CTRL1_A register description ODR [3:0] is used to set the power mode and ODR selection. The following table lists the bit settings for power-down mode and each available frequency. Table 29. Module_8bit_A register Module_7 Module_6 Module_5 Module_4 Module_3 Module_2 Module_1 Module_0 Module [7:0] Module output value (8-bit). Default value: 0 Table 31. WHO_AM_I_A register default values 01000011 ODR3 ODR2 ODR1 ODR0 FS1 FS0 HF_ODR BDU ODR [3:0] Output data rate & power mode selection. Default value: 0000 (see Table 34) FS [1:0] Full-scale selection. Default value: 00 (00: ±2 g; 01: ±16 g; 10: ±4 g; 11: ±8 g) HF_ODR High-frequency ODR mode enable. Default value: 0 BDU Block data update. Default value: 0 (0: continuous update; 1: output registers not updated until MSB and LSB read) Table 34. ODR register setting: power down (PD) and low power (LP) ODR[3:0] HF_ODR ODR selection [Hz] Bit resolution Mode 0000 - - - PD 1000 - 1 10 LP 1001 - 12.5 10 LP 1010 - 25 10 LP |
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