CS47L15 datasheet(37/279 Pages) CIRRUS

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DS1137F2

CS47L15

4.2 Input Signal Path

The IN1 analog input paths can be configured for low-power operation, ideal for always-on applications. If the IN1 signal

path is configured for analog input, low-power operation can be selected as described in Section 4.2.7.1.

The IN2 analog input path supports mono input only. The IN2 analog input PGA gain is fixed at 14 dB.

If the IN1 input signal path is configured for digital (DMIC) input, the voltage reference for the DMICDAT/DMICCLK pins is

selectable using IN1_DMIC_SUP; the interface is referenced to MICVDD or MICBIAS1. The voltage reference selection

controls the digital logic thresholds for the DMICDAT/DMICCLK pins (see Table 3-10)—it should be set equal to the

applicable power supply of the respective microphones.

If the IN1 input signal path is configured for digital input, the DMICCLK frequency can be configured using the IN1_OSR

field.

If the IN2 input signal path is configured for digital input, the interface clocking frequency is configured using the IN2_OSR

field. The IN2_OSR field must select the same frequency as the OUT5_OSR bit (see Table 4-55).

The input signal paths are configured using the fields described in Table 4-4.

Table 4-4. Input Signal Path Configuration

Bit

Label

Default

Description

R780 (0x030C)

HPF_Control

2:0 IN_HPF_

CUT[2:0]

010

Input Path HPF Select. Controls the cut-off frequency of the input path HPF circuits.

000 = 2.5 Hz

001 = 5 Hz

010 = 10 Hz

011 = 20 Hz

100 = 40 Hz

All other codes are reserved

R784 (0x0310)

IN1L_Control

IN1L_HPF

Input Path 1 (Left) HPF Enable

0 = Disabled

1 = Enabled

12:11 IN1_DMIC_

SUP[1:0]

Input Path 1 DMIC Reference Select (sets the DMICDAT and DMICCLK logic levels)

00 = MICVDD

01 = MICBIAS1

All other codes are reserved

IN1_MODE

Input Path 1 Mode

0 = Analog input

1 = Digital input

7:1 IN1L_PGA_

VOL[6:0]

0x40 Input Path 1 (Left) PGA Volume (applicable to analog inputs only)

0x00 to 0x3F = Reserved

0x40 = 0 dB

0x41 = 1 dB

0x42 = 2 dB

… (1-dB steps)

0x5F = 31 dB

0x60 to 0x7F = Reserved

R785 (0x0311)

ADC_Digital_

Volume_1L

14:13 IN1L_

SRC[1:0]

Input Path 1 (Left) Source

00 = Differential (IN1ALP–IN1ALN)

01 = Single-ended (IN1ALP)

10 = Differential (IN1BP–IN1BN)

11 = Single-ended (IN1BP)

R786 (0x0312)

DMIC1L_Control

10:8 IN1_

OSR[2:0]

101

Input Path 1 Oversample Rate Control

If analog input is selected, this field must be set to 101 (default).

If digital input is selected, this field controls the DMICCLK frequency.

010 = 384 kHz

011 = 768 kHz

100 = 1.536 MHz

101 = 3.072 MHz

110 = 6.144 MHz

All other codes are reserved

R788 (0x0314)

IN1R_Control

IN1R_HPF

Input Path 1 (Right) HPF Enable

0 = Disabled

1 = Enabled

12:11 IN1_

DMICCLK_

SRC[1:0]

Input Path 1 DMIC Clock Source

00 = DMICCLK1

All other codes are reserved.

If digital input is selected, this field must be 00. Under default conditions, this field is locked

and cannot be written. To change the value of this field, the user key must be set before

writing to IN1_DMICCLK_SRC.

7:1 IN1R_PGA_

VOL[6:0]

0x40 Input Path 1 (Right) PGA Volume (applicable to analog inputs only)

0x00 to 0x3F = Reserved

0x40 = 0 dB

0x41 = 1 dB

0x42 = 2 dB

… (1-dB steps)

0x5F = 31 dB

0x60 to 0x7F = Reserved

R789 (0x0315)

ADC_Digital_

Volume_1R

14:13 IN1R_

SRC[1:0]

Input Path 1 (Right) Source

00 = Differential (IN1ARP–IN1ARN)

01 = Single-ended (IN1ARP)

10 = Differential (IN1BRP–IN1BRN)

11 = Single-ended (IN1BRP)

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