CS47L15 datasheet(82/279 Pages) CIRRUS

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DS1137F2

CS47L15

4.4 DSP Firmware Control

4.4.3.2 DSP Clocking

Clocking is required for the DSP processing block, when executing software or when supporting DMA functions. (Note that

clocking is not required for access to the firmware registers by the host processor.)

Clocking within the DSP is enabled and disabled automatically, as required by the DSP core and DMA channel status.

In normal operating conditions, the clock source for the DSP is derived from DSPCLK. See Section 4.13 for details of how

to configure DSPCLK. See Section 4.4.3.4 for supported clocking configurations when DSPCLK is not enabled.

The clock frequency for the DSP is selected using DSP1_CLK_FREQ_SEL. The DSP clock frequency must be less than

or equal to the DSPCLK frequency.

The DSP1_CLK_FREQ_STS field indicates the clock frequency for the DSP core. This can be used to confirm the clock

frequency, in cases where code execution has a minimum clock frequency requirement. The DSP1_CLK_FREQ_STS

field is only valid when the core is running code; typical usage of this field would be for the DSP core itself to read the clock

status and to take action as applicable, in particular, if the available clock does not meet the application requirements.

Note that, depending on the DSPCLK frequency and the available clock dividers, the DSP1 clock frequency may differ

from the selected clock. In most cases, the DSP1 clock frequency equals or exceeds the requested frequency. A lower

frequency is implemented if limited by either the DSPCLK frequency or the maximum DSP1 clocking frequency.

The DSPCLK configuration provides input to the interrupt control circuit and can be used to trigger an interrupt event when

the DSP1 clock frequency is less than the requested frequency; see Section 4.12.

4.4.3.3 DSP Code Execution

After the DSP firmware has been loaded, and the clocks configured, the DSP block is enabled by setting DSP1_CORE_

ENA. When the DSP is configured and enabled, the firmware execution can be started by writing 1 to DSP1_START.

Alternative methods to trigger the firmware execution can also be configured using the DSP1_START_IN_SEL field.

Using the DSP1_START_IN_SEL field, the DSP firmware execution can be linked to the respective DMA function, the

IRQ2 status, or to the FIFO status in one of the event loggers:

• DMA function: firmware execution commences when all enabled DSP input (WDMA) channel buffers have been

filled, and all enabled DSP output (RDMA) channel buffers have been emptied

• IRQ2: firmware execution commences when one or more of the unmasked IRQ2 events has occurred

• Event logger status: firmware execution commences when the FIFO not-empty status is asserted within the

respective event logger

To enable firmware execution on the DSP block, the DSP1_CORE_ENA bit must be set. Note that the usage of the DSP1_

START bit may vary depending on the particular firmware that is being executed: in some applications (e.g., when an

alternative trigger is selected using DSP1_START_IN_SEL), writing to the DSP1_START bit is not required.

4.4.3.4 DSP Operation without DSPCLK

In normal operating conditions, the clock source for the DSP block is derived from DSPCLK. The CS47L15 also supports

DSP operation when DSPCLK is not enabled; this provides capability for always-on DSP applications.

The alternative clock source, for DSP clocking without DSPCLK, is the always-on FLL (FLL_AO). The FLL_AO output

frequency range is approximately 45–50 MHz and is suitable for low-speed DSP clocking requirements.

The default FLL_AO settings are configured to provide a 49.152-MHz output, suitable for use as the always-on DSP clock

source. Note that the FLL_AO control registers must always hold valid settings—either enabled and locked to an input

reference clock, or else configured in FLL Hold Mode. See Section 4.13.9 for details of FLL_AO.

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