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CS47L15 датащи(PDF) 39 Page - Cirrus Logic |
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CS47L15 датащи(HTML) 39 Page - Cirrus Logic |
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39 / 279 page ![]() DS1137F2 39 CS47L15 4.2 Input Signal Path Table 4-7 lists the input signal path digital volume settings. Table 4-6. Input Signal Path Digital Volume Control Register Address Bit Label Default Description R777 (0x0309) Input_Volume_ Ramp 6:4 IN_VD_RAMP[2:0] 010 Input Volume Decreasing Ramp Rate (seconds/6 dB) This field should not be changed while a volume ramp is in progress. 000 = 0 ms 001 = 0.5 ms 010 = 1 ms 011 = 2 ms 100 = 4 ms 101 = 8 ms 110 = 15 ms 111 = 30 ms 2:0 IN_VI_RAMP[2:0] 010 Input Volume Increasing Ramp Rate (seconds/6 dB) This field should not be changed while a volume ramp is in progress. 000 = 0 ms 001 = 0.5 ms 010 = 1 ms 011 = 2 ms 100 = 4 ms 101 = 8 ms 110 = 15 ms 111 = 30 ms R785 (0x0311) ADC_Digital_ Volume_1L 9 IN_VU See Footnote 1 Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Signal Paths Volume and Mute settings to be updated simultaneously 8 IN1L_MUTE 1 Input Path 1 (Left) Digital Mute 0 = Unmute 1 = Mute 7:0 IN1L_VOL[7:0] 0x80 Input Path 1 (Left) Digital Volume (see Table 4-7 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64dB 0x01 = –63.5dB … (0.5-dB steps) 0x80 = 0 dB … (0.5-dB steps) 0xBF = +31.5 dB 0xC0 to 0xFF = Reserved R789 (0x0315) ADC_Digital_ Volume_1R 9 IN_VU See Footnote 1 Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Signal Paths Volume and Mute settings to be updated simultaneously 8 IN1R_MUTE 1 Input Path 1 (Right) Digital Mute 0 = Unmute 1 = Mute 7:0 IN1R_VOL[7:0] 0x80 Input Path 1 (Right) Digital Volume (see Table 4-7 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64dB 0x01 = –63.5dB … (0.5-dB steps) 0x80 = 0 dB … (0.5-dB steps) 0xBF = +31.5 dB 0xC0 to 0xFF = Reserved R793 (0x0319) ADC_Digital_ Volume_2L 9 IN_VU See Footnote 1 Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Signal Paths Volume and Mute settings to be updated simultaneously 8 IN2L_MUTE 1 Input Path 2 (Left) Digital Mute 0 = Unmute 1 = Mute 7:0 IN2L_VOL[7:0] 0x80 Input Path 2 (Left) Digital Volume (see Table 4-7 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64dB 0x01 = –63.5dB … (0.5-dB steps) 0x80 = 0 dB … (0.5-dB steps) 0xBF = +31.5 dB 0xC0 to 0xFF = Reserved R797 (0x031D) ADC_Digital_ Volume_2R 9 IN_VU See Footnote 1 Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Signal Paths Volume and Mute settings to be updated simultaneously 8 IN2R_MUTE 1 Input Path 2 (Right) Digital Mute 0 = Unmute 1 = Mute 7:0 IN2R_VOL[7:0] 0x80 Input Path 2 (Right) Digital Volume (see Table 4-7 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64dB 0x01 = –63.5dB … (0.5-dB steps) 0x80 = 0 dB … (0.5-dB steps) 0xBF = +31.5 dB 0xC0 to 0xFF = Reserved 1. Default is not applicable to these write-only bits |
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