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Internally resets chip if not periodically reloaded.

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The watchdog timer has lock register to prevent rogue software from disabling the

watchdog timer functionality.

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The watchdog timer clock(WDTCLK) and system clock(PCLK) are synchronous.

3.15 Real-time clock (RTC)

The real-timer clock (RTC) is an independent BCD timer/counter. The RTC provides a timer-

of-day clock/calendar with programmable alarm interrupt.

Calendar with year, month, day, weekday, hours, minutes, and seconds

Programmable alarm with interrupt function

3.15.1

RTC clock

RTC Clock (RTCCLK) can be selected among several clocks (32768Hz oscillator, MCLK, RCLK,

OCLK). Please refer to the Clock Reset Generator chapter for configuring the clock.

If the 32768Hz oscillator clock is used, the divider generates 1 Hz clock internally.

If the DIVRST (Bit[1] of RTC Control Register ) value is high, the RTC Divider is cleared. If the

DIVRST value is low, the divider operates.

3.15.2

RTC interrupt

RTC has two kinds of interrupt source, Counter Interrupt and Alarm Interrupt.

Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.

There are following Counter Interrupts: Second, Minute, Hour, Day (Day of Week), Date (Day

of Month) and Year.

Each bit of RTCINTM (Interrupt Mask Register) can disable or enable interrupt for each Counter

Interrupt.

Alarm Interrupt can be generated when the Alarm matches with Counter.

3.16 Universal asynchronous receiver/transmitter (UART)

The device embeds three universal asynchronous receivers/transmitters (UART0, UART1,

UART2) which communicate at speeds of up to 460.8 Kbit/s.

The UART supports synchronous one-way communication, half-duplex single wire

communication, and UART0,1 supports multiprocessor communications(CTS/RTS) but UART2

unsupported multiprocessor communications UART2 is called the SUART(Simple UART).

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Serial-to-parallel conversion on data received from a peripheral device

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Parallel-to-serial conversion on data transmitted to the peripheral device

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Data size of 5,6,7 and 8 its

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One or two stop bits

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Even, odd, stick, or no-parity bit generation and detection

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Support of hardware flow control

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Programmable FIFO disabling for 1-byte depth.

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Programmable use of UART or IrDA SIR input/output

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False start bit detection

UART bidirectional communication requires a minimum of two pins: RX, TX

The frame are comprised of:



An Idle Line prior to transmission or reception

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A start bit

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A data word (8 or 9 bits) least significant bit first

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