W7500P datasheet(12/38 Pages) WIZNET

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oscillator clock circuit. In W7500x, there is no supported ��

�� for External oscillator clock (see

Figure 3).

For ��

��1 and ��2, it is recommended to use external ceramic capacitors in the 5 pF to

25 pF range(typ.) and are usually the same size, designed for application, and selected to

match the requirements of the crystal or resonator (see Figure 3).

Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

1 ��

�� value depends on the crystal characteristics

Figure 3 Typical application with an 8 MHz crystal

3.6.2

RC oscillator clock

RC oscillator clock (RCLK) signal is generated from an internal 8MHz RC oscillator.

RC oscillator has the advantage of providing a clock source at low cost (no external

components). However the RC oscillator is less accurate than the external crystal or ceramic

resonator.

Accuracy : 1% at TA= 25oC (User don’t need to calibration)

3.6.3

PLL

The internal PLL can be used to multiply the External Oscillator Clock (OCLK) or RC Oscillator

Clock (RCLK). PLL input can be selected by register.

PLL output clock can be generated by following the equations below.



FOUT = FIN x M / N x 1 / OD



Where:



M = M[5] x 25 + M[4] x 24 + M[3] x 23 + M[2] x 22 + M[1] x 2 + M[0] x 1



N = N[5] x 25 + N[4] x 24 + N[3] x 23 + N[2] x 22 + N[1] x 2 + N[0] x 1



OD = 2 (2 x OD[1]) x 2 (1 x OD[0])

3.6.4

Generated clock

Each generated clock source can be selected among 3 clock source as independent by each

clock source select register.



PLL output clock (MCLK)



Internal 8MHz RC oscillator clock (RCLK)



External oscillator clock (8MHz ~ 24MHz) (OCLK)



Each generated clock has own prescaler which can be selected individually by each

prescale value register.



FCLK, SSPCLK, UARTCLK : 1/1, 1/2, 1/4, 1/8

1 ��

�� value depends on the crystal characteristics

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