поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

T1024 датащи(PDF) 42 Page - Freescale Semiconductor, Inc

номер детали T1024
подробное описание детали  QorIQ T1024 Reference Design Board
PDF  49 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

T1024 датащи(HTML) 42 Page - Freescale Semiconductor, Inc

Back Button T1024 Datasheet HTML 38Page - Freescale Semiconductor, Inc T1024 Datasheet HTML 39Page - Freescale Semiconductor, Inc T1024 Datasheet HTML 40Page - Freescale Semiconductor, Inc T1024 Datasheet HTML 41Page - Freescale Semiconductor, Inc T1024 Datasheet HTML 42Page - Freescale Semiconductor, Inc T1024 Datasheet HTML 43Page - Freescale Semiconductor, Inc T1024 Datasheet HTML 44Page - Freescale Semiconductor, Inc T1024 Datasheet HTML 45Page - Freescale Semiconductor, Inc T1024 Datasheet HTML 46Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 42 / 49 page
background image
3.1.12 Miscellanies Control and Status Register
(CPLD_MISCCSR)
Address: 0h base + 17h offset = 17h
Bit
0
1
2
3
4
5
6
7
Read
Reserved
SLEEP_EN
REQ_MD
TDMR_PRS
PEX_PRS
Reserved
TEST_SEL_
N
Write
Reset
0
0
1
1
x*
x*
0
x*
* Notes:
x depends on whether TDM or PCIe card is plugged in.x = Undefined at reset.
•
CPLD_MISCCSR field descriptions
Field
Description
0
-
This field is reserved.
1
SLEEP_EN
Deep sleep enable bit
0
Normal operation.
1
Before enter deep sleep mode, set ‘1’ to this bit, after exit deep sleep mode, set ‘0’ to this bit.
2–3
REQ_MD
00
No reset occurs when HRESET_REQ triggered.
01
HRESET occurs when HRESET_REQ triggered.
10
NA
11
PORESET occurs when HRESET_REQ triggered.
4
TDMR_PRS
0
TDM riser card not present.
1
TDM riser card present.
5
PEX_PRS
0
PCIe x1 card not present.
1
PCIe x1 card present.
6
-
This field is reserved.
7
TEST_SEL_N
0
TEST_SEL_N pin status is 0.
0
TEST_SEL_N pin status is 1.
3.1.13 Boot Configuration Override Register (CPLD_BOOTOR)
Address: 0h base + 18h offset = 18h
Bit
0
1
2
3
Read
Reserved
Write
Reset
0
0
0
0
Bit
4
5
6
7
Read
Reserved
PCIE_2.5G_OR
BOOT_OR
Write
Reset
0
0
0
0
CPLD Memory Map/Register Definition
QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015
42
Freescale Semiconductor, Inc.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com