T1024 datasheet(40/49 Pages) FREESCALE

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3.1.8 Flash Control and Status Register (CPLD_FLHCSR)

Address: 0h base + 13h offset = 13h

Bit

Read BOOT_SEL

BANK_OR

SW_BANK_

SEL0

SW_BANK_

SEL1

SW_BANK_

SEL2

BANK_

SEL0

BANK_

SEL1

BANK_

SEL2

Write

Reset

* Notes:

x depends DIP switch setting.x = Undefined at reset.

•

CPLD_FLHCSR field descriptions

Field

Description

BOOT_SEL

Boot from 16bit NOR flash.

Boot from 8bit NAND flash.

BANK_OR

NOR flash bank select from CPLD override disable.

NOR flash bank select from CPLD override enable.

SW_BANK_SEL0

NOR flash bank select bit0 of switch status is 0.

NOR flash bank select bit0 of switch status is 1.

SW_BANK_SEL1

NOR flash bank select bit1 of switch status is 0.

NOR flash bank select bit1 of switch status is 1.

SW_BANK_SEL2

NOR flash bank select bit2 of switch status is 0.

NOR flash bank select bit2 of switch status is 1.

BANK_SEL0

NOR flash bank select bit0 set 0.

NOR flash bank select bit0 set 1.

BANK_SEL1

NOR flash bank select bit1 set 0.

NOR flash bank select bit1 set 1.

BANK_SEL2

NOR flash bank select bit2 set 0.

NOR flash bank select bit2 set 1.

3.1.9 Fan Control and Status Register (CPLD_FANCSR)

Address: 0h base + 14h offset = 14h

Bit

Read

Reserved

FAN_PWM

Write

Reset

CPLD Memory Map/Register Definition

QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015

Freescale Semiconductor, Inc.

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