SLK2511

OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLLS522A – JUNE 2002 – REVISED OCTOBER 2002

6

POST OFFICE BOX 655303

Terminal Functions(Continued)

control/status pins (continued)

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

PAR_VALID

2

TTL output

Parity checker output. The internal parity checker on the parallel side of the transmitter

checks for even parity. If there is a parity error, the pin is pulsed low for 2 clock cycles.

PRBSPASS

42

TTL output

PRBS test result. This pin reports the status of the PRBS test results (high = pass).

When PRBSEN is disabled, the PRBSPASS pin is set low. When PRBSEN is enabled

and a valid PRBS is received, then the PRBSPASS pin is set high.

REFCLKSEL

40

TTL input (with pulldown)

Reference clock select. The device can accept a clock frequency of 155.52 MHz or

622.08 MHz, which is selected by this pin (0 = 622.08-MHz mode and 1 = 155.52-MHz

mode).

SPILL

49

TTL output

TX FIFO collision output

voltage supply and reserved pins

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

GND

1, 6, 19, 23, 26,

28, 30, 31, 33

Ground

Digital logic ground

GNDA

10, 13

Ground

Analog ground

GNDLVDS

61, 69, 76, 77,

89, 93, 96, 100

Ground

LVDS ground

GNDPLL

12

Supply

PLL ground

RSVD

52

Reserved

This pin needs to be tied to ground or left floating for normal operation.

VDD

3, 22, 25, 29,

32, 35, 50

Supply

Digital logic supply voltage (2.5 V)

VDDA

7, 16

Supply

Analog voltage supply (2.5 V)

VDDLVDS

62, 72, 75, 78,

90, 91, 92, 97

Supply

LVDS supply voltage (2.5 V)

VDDPLL

11

Supply

PLL voltage supply (2.5 V)