STM8S datasheet(403/467 Pages) STMICROELECTRONICS

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RM0016

Controller area network (beCAN)

427

23.11.3

CAN transmit status register (CAN_TSR)

Address offset: 0x02

Reset value: 0x00

Bit 2 ERRI Error Interrupt

This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the

corresponding interrupt in the CAN_EIER is enabled. Setting this bit generates a status change

interrupt if the ERRIE bit in the CAN_EIER register is set.

This bit is cleared by software writing 1.

Bit 1 SLAK Sleep Acknowledge

This bit is set by hardware and indicates to the software that the CAN hardware is now in sleep

mode. This bit acknowledges the sleep mode request from the software (set SLEEP bit in

CAN_MCR register).

This bit is cleared by hardware when the CAN hardware has exited Sleep mode. Sleep mode is

exited when the SLEEP bit in the CAN_MCR register is cleared. Please refer to the AWUM bit of the

CAN_MCR register description for detailed information for clearing SLEEP bit.

Bit 0 INAK Initialization Acknowledge

This bit is set by hardware and indicates to the software that the CAN hardware is now in

initialization mode. This bit acknowledges the initialization request from the software (set INRQ bit in

CAN_MCR register).

This bit is cleared by hardware when the CAN hardware has exited initialization mode and is now

synchronized on the CAN bus. To be synchronized the hardware has to monitor a sequence of 11

consecutive recessive bits on the CAN RX signal.

654

3210

Reserved

TXOK2

TXOK1

TXOK0

Reserved

RQCP2

RQCP1

RQCP0

rc_w1

Bit 7 Reserved.

Bit 6 TXOK2 Transmission OK for mailbox 2

This bit is set by hardware when the transmission request on mailbox 2 has been completed

successfully. Please refer to Figure 146.

This bit is cleared by hardware when mailbox 2 is requested for transmission or when the software

clears the RQCP2 bit.

Bit 5 TXOK1 Transmission OK for mailbox 1

This bit is set by hardware when the transmission request on mailbox 1 has been completed

successfully. Please refer to Figure 146.

This bit is cleared by hardware when mailbox 1 is requested for transmission or when the software

clears the RQCP1 bit.

Bit 4 TXOK0 Transmission OK for mailbox 0

This bit is set by hardware when the transmission request on mailbox 0 has been completed

successfully. Please refer to Figure 146.

This bit is cleared by hardware when mailbox 1 is requested for transmission or when the software

clears the RQCP0 bit.

Bit 3 Reserved.

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