STM8S datasheet(367/467 Pages) STMICROELECTRONICS

367 / 467 page

DocID14587 Rev 14

367/467

RM0016

Universal asynchronous receiver transmitter (UART)

377

22.7.6

Control register 2 (UART_CR2)

Address offset: 0x05

Reset value: 0x00

Bit 2 PCEN: Parity control enable.

–UART Mode

This bit selects the hardware parity control (generation and detection). When the parity control is

enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity

is checked on the received data. This bit is set and cleared by software. Once it is set, PCEN is

active after the current byte (in reception and in transmission).

0: Parity control disabled

1: Parity control enabled

– LIN slave mode

This bit enables the LIN identifier parity check while the UART is in LIN slave mode.

0: Identifier parity check disabled

1: Identifier parity check enabled

Bit 1 PS: Parity selection.

This bit selects the odd or even parity when the parity generation/detection is enabled (PCEN bit set)

in UART mode. It is set and cleared by software. The parity will be selected after the current byte.

0: Even parity

1: Odd parity

Bit 0 PIEN: Parity interrupt enable.

This bit is set and cleared by software.

0: Parity interrupt disabled

1: Parity interrupt is generated whenever PE=1 in the UART_SR register

654

3210

TIEN

TCIEN

RIEN

ILIEN

TEN

REN

RWU

SBK

Bit 7 TIEN: Transmitter interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An UART interrupt is generated whenever TXE=1 in the UART_SR register

Bit 6 TCIEN: Transmission complete interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An UART interrupt is generated whenever TC=1 in the UART_SR register

Bit 5 RIEN: Receiver interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An UART interrupt is generated whenever OR=1 or RXNE=1 in the UART_SR register

Bit 4 ILIEN: IDLE Line interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An UART interrupt is generated whenever IDLE=1 in the UART_SR register

STM8S датащи(PDF) 367 Page - STMicroelectronics

STM8S датащи(HTML) 367 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL