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AX68004LF датащи(PDF) 48 Page - ASIX Electronics Corporation

номер детали AX68004LF
подробное описание детали  2/4-Port USB KVM Switch SoC
PDF  57 Pages
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производитель  ASIX [ASIX Electronics Corporation]
домашняя страница  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX68004LF датащи(HTML) 48 Page - ASIX Electronics Corporation

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2/4-Port USB KVM Switch SoC
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4.5.4 I2C Interface Timing
Symbol
Parameter
Min
Typ
Max
Units
Fclk
SCL clock frequency
-
-
100,
400
KHz
Thd_sta
Hold time of (repeated) START condition. After this period,
the first clock pulse is generated
-
2
-
Tprsc2
Thigh
High period of the SCL clock
-
2
-
Tprsc
Tlow
Low period of the SCL clock
-
3
-
Tprsc
Tsu_sta
Setup time for a repeated START condition
-
2
-
Tprsc
Tsu_dat
Data Setup time
-
1
-
Tprsc
Thd_dat
Data hold time
-
2
-
Tprsc
Tsu_sto
Setup time for STOP condition
-
3
-
Tprsc
Tbuf
Bus free time between a STOP and START condition
-
4
-
Tprsc
Table 4-1: I2C Master Controller Timing Table
Symbol
Parameter
Min
Typ
Max
Units
Fclk
SCL clock frequency
-
-
380
KHz
Thd_sta
Hold time of (repeated) START condition. After this period,
the first clock pulse is generated
1
-
-
Tsys_clk3
Thigh
High period of the SCL clock in Standard mode
4
-
-
µs
High period of the SCL clock in Fast mode
0.6
-
-
µs
Tlow
Low period of the SCL clock
0.4
-
-
µs
Tsu_sta
Setup time for a repeated START condition
1
-
-
Tsys_clk
Tsu_dat
Data Setup time
3
-
-
Tsys_clk
Thd_dat
Data hold time
0.4
-
-
µs
Tsu_sto
Setup time for STOP condition
1
-
-
Tsys_clk
Tbuf
Bus free time between a STOP and START condition
12
-
-
Tsys_clk
Table 4-2: I2C Slave Controller Timing Table
2 Tprsc = 1 / Fprsc, where Fprsc = Operating system clock frequency / (PRER + 1). The PRER is I2C Clock
Prescale Register.
3 Tsys_clk = 10.416/20.833ns for 96/48 MHz operating system clock.
Tsu_sto
Thd_sta
Tsu_sta
Thd_dat
Tlow
Thigh
Tlow
Tsu_dat
Thigh
Thd_sta
Tbuf
Tbuf
SDA
SCL



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