AX68004LF datasheet(19/57 Pages) ASIX

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AX6800x

2/4-Port USB KVM Switch SoC

Table 1-7: UART 0 & Buzzer Pin Description

UART 0 Interface

Pin Name

Type

Pin No

Pin Description

100

RXD0

B5/4m/PU 60

UART 0 serial Receive Data.

TXD0

O5/4m

UART 0 serial Transmit Data.

BUZZER

O5/4m

Buzzer

(5).

Note 5: To enable these multi-function pins, please set BUZZER_PSEL = 0 in HWCFG offset 0x003 or

BUZZER_PSEL = 1 but MP1_7_PSEL = 1 in HWCFG offset 0x001.

Table 1-8: GPIO Pin Description

GPIO Interface

Pin Name

Type

Pin No

Pin Description

100

P0[7:0]

B5/4m/PU 34, 35, 21,

38, 13, 11,

10, 9

(2, 1, 5, 4,

39, 41, 40,

42)

53, 55, 35,

60, 20, 17,

15, 12

(4, 2, 7, 6, 62,

64, 63, 65)

General Purpose Input/ Output Pins Port 0 (6).

To enable these multi-function pins, please set

MP0_10/32/74_PSEL = 0 in HWCFG offset 0x001. P0 has

two pinout options and the parenthesis indicates the 2nd

option, enabled by setting MP0_10/32/74_PSEL = 1,

USB_D0/D1_PSEL = 1 and, I2C_U0/U1_PSEL = 1.

P1[7:0]

B5/4m/PU -

39, 41, 43,

46, 18, 16,

14, 9

General Purpose Input/ Output Pins Port 1 (6).

To enable these multi-function pins, please set

MP1_10/32/54/6/7_PSEL = 0 in HWCFG offset 0x001.

P2[7:0]

B5/4m/PU 14, 15, 16,

17, 19, 20,

36, 23

22, 23, 25,

28, 31, 33,

57, 38

General Purpose Input/ Output Pins Port 2 (6).

To enable these multi-function pins, please set

MP2_0/31/54/76_PSEL = 0 in HWCFG offset 0x002.

P3[7:0]

B5/4m/PU -

21, 24, 26,

27, 29, 32,

34, 36

General Purpose Input/ Output Pins Port 3 (6).

To enable these multi-function pins, please set

MP3_30/74_PSEL = 0 in HWCFGS offset 0x002.

Note 6: Due to internal weak pull-up, user may add stronger external pull-up resistors for these GPIO pins, if

necessary.

Table 1-9: Interrupt Pin Description

Interrupt Interface

Pin Name

Type

Pin No

Pin Description

100

INT0

I5/PU

CPU INTerrupt 0 inputs, active low or falling edge trigger

(7).

Note 7: To enable these multi-function pins, please set MP1_6_PSEL = 1 in HWCFG offset 0x001.

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