AX68004LF datasheet(28/57 Pages) ASIX

28 / 57 page

AX6800x

2/4-Port USB KVM Switch SoC

2.12 GPIOs

The CPU of AX6800x supports four 8-bit bi-directional, open-drain, general purpose input and output ports,

namely, P0[7:0], P1[7:0], P2[7:0] and P3[7:0]. Each port bit can be individually accessed by bit addressable

instructions.

For the special application, like push button, P0 and P2 support de-bounce and interrupt function which can be

programmed to detect the rising, falling edge and both interrupt event. Each bit in these two ports support the

wake-up function also. It can wake-up CPU from STOP or deep sleep mode. The function can be enabled or

disabled separately per bit.

2.13 Buzzer Controller

The Buzzer Controller of AX6800x supports 8 kinds of frequency and 5 duration times can be selected. CPU can

start the buzzer sound and will be interrupted when the duration is time up.

2.14 I2C Controller

The I2C Controller of AX6800x consists of an I2C master controller to support communication to external I2C

devices (Monitor), 2/4 I2C slave controllers to support communication to external Host with I2C master (PC).

I2C master controller supports the auto-detection function to detect the external monitor has been

plugged/un-plugged and the auto-load function to load the EDID contents from external monitor to internal 32KB

SRAM automatically.

Each I2C slave controller also supports the DMA function to read EDID information from 32KB SRAM to

external Host automatically.

2.15 High Speed SPI Controller

The High Speed Serial Peripheral Interface (SPI) Controller provides a full-duplex, synchronous serial

communication interface (4 wires) to flexibly work with numerous SPI peripheral devices or microcontroller with

SPI master. The High Speed SPI Controller consists of a High Speed SPI master controller with 3 slave select pins,

MSS[2:0], to connect up to 7 SPI devices and a High Speed SPI slave controller to support communication with

external microcontroller with SPI master.

For high performance applications, the High Speed SPI Controller in master and slave mode both support

burst-type transfer for receiving data from SPI bus to CPU xDATA memory via DMA write access (SPI RX

DMA) and for transmitting data from xDATA memory to SPI bus via DMA read access (SPI TX DMA).

AX68004LF датащи(PDF) 28 Page - ASIX Electronics Corporation