CS61583 datasheet(37/44 Pages) CIRRUS

37 / 44 page

Crystal Oscillator

A crystal oscillator may be inserted at socket U4

in the orientation indicated by the silkscreen.

Header J14 must be jumpered in the "OSC"

position to provide connectivity to the REFCLK

pin of the CS61583. The SW2 switch position

labeled "1XCLK" must be open (logic 0) for 8-X

clock operation or closed (logic 1) for 1-X clock

operation.

External Reference

An external reference may be provided at the

REFCLK BNC input. Header J14 must be

jumpered in the "REFCLK" position to provide

connectivity

the

REFCLK

the

CS61583. The SW2 switch position labeled

"1XCLK" must be open (logic 0) for 8-X clock

operation or closed (logic 1) for 1-X clock

operation.

BUFFERING

Buffers U2 and U3 provide additional drive

capability for the BNC inputs and outputs. The

buffer outputs are filtered with an RC network to

reduce the transients caused by buffer switching.

JTAG ACCESS

The CS61583 implements JTAG boundary scan

to support board-level testing. Interface port J56

provides access to the four JTAG pins on the

CS61583. The J-TMS pin of the CS61583 is

pulled-down by resistor R28 to disable boundary

scan unless the pin is externally pulled high

using the interface port.

TRANSFORMER SELECTION

The evaluation board is supplied from the

factory

with

Pulse

Engineering

PE-65388

transformers installed at locations T1-T4. They

are socketed to permit the evaluation of other

transformers.

LINE PROTECTION EVALUATION

Several optional resistor and diode locations on

the transmit and receive line interface allow for

the installation and evaluation of various types

of protection circuitry. Each location is drilled

with 60 mil vias to permit the installation of

sockets. These sockets can be obtained from

McKenzie at (510) 651-2700 by requesting part

#PPC-SIP-1X32-620C and are identical to the

socket type installed at various resistor locations

on the board. They allow the line protection

circuitry to be easily changed during testing.

Note that the traces forming shorts between the

socket locations on the line interface may need

to be cut prior to protection circuitry installation.

PROTOTYPING AREA

Four prototyping areas with power supply and

ground

connections

are

provided

the

evaluation board. These areas can be used to

develop and test a variety of additional circuits

such as framer devices, system synchronizer

PLLs, or specialized interface logic.

EVALUATION HINTS

1. The orientation of pin 1 for the CS61583 is

labeled "1" on the left side of the socket U7.

2. A jumper must be placed on header J10 when

using the CDB61583.

3. Component locations R3-R4, R14-R15, C1,

and C12 must have the correct values installed

according to the application. All the necessary

components are included with the evaluation

board.

CDB61583

DB172PP1

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