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CS61583 датащи(PDF) 18 Page - Cirrus Logic

номер детали CS61583
подробное описание детали  DUAL T1/E1 LINE INTERFACE
PDF  44 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS61583 датащи(HTML) 18 Page - Cirrus Logic

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instruction register and all test data registers re-
tain their previous state. When J-TMS is high
and a rising edge is applied to J-TCK, the con-
troller moves to the Select-DR state.
Select-DR-Scan State
This is a temporary controller state.
The test
data register selected by the current instruction
retains its previous state. If J-TMS is held low
and a rising edge is applied to J-TCK when in
this state, the controller moves into the Capture-
DR state and a scan sequence for the selected
test data register is initiated. If J-TMS is held
high and a rising edge applied to J-TCK, the
controller moves to the Select-IR-Scan state.
The instruction does not change in this state.
Capture-DR State
In this state, the Boundary Scan Register cap-
tures input pin data if the current instruction is
EXTEST or SAMPLE/PRELOAD.
The other
test data registers, which do not have parallel in-
put, are not changed.
The instruction does not change in this state.
When the TAP controller is in this state and a
rising edge is applied to J-TCK, the controller
enters the Exit1-DR state if J-TMS is high or the
Shift-DR state if J-TMS is low.
Shift-DR State
In this controller state, the test data register con-
nected between J-TDI and J-TDO as a result of
the current instruction shifts data on stage to-
ward its serial output on each rising edge of
J-TCK.
The instruction does not change in this state.
When the TAP controller is in this state and a
rising edge is applied to J-TCK, the controller
enters the Exit1-DR state if J-TMS is high or re-
mains in the Shift-DR state if J-TMS is low.
Exit1-DR State
This is a temporary state. While in this state, if
J-TMS is held high, a rising edge applied to J-
T C K c au s es t h e c o n t rol ler to enter the
Update-DR state, which terminates the scanning
process. If J-TMS is held low and a rising edge
is applied to J-TCK, the controller enters the
Pause-DR state.
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
1
0
0
1
1
0
10
1
1
0
1
0
0
1
0
1
0
0
1
10
1
1
0
1
0
0
1
0
1
0
Figure 12. TAP Controller State Diagram
CS61583
18
DS172PP5



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