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CS5541 датащи(PDF) 12 Page - Cirrus Logic

номер детали CS5541
подробное описание детали  Low-power, High-Voltage, 24-Bit Delta-Sigma ADC
PDF  26 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5541 датащи(HTML) 12 Page - Cirrus Logic

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CS5541
12
DS500PP1
2.3 Power Supply Arrangements
The CS5541 is designed to operate with a total sup-
ply voltage of 3.0 V ± 5%. For maximum flexibility
separate pins are provided for VA+, VA-, VD+,
and DGND, which is especially useful with ground
referenced input signals.
Figure 9 illustrates the CS5541 connected with a
single +3.0 V supply for both the analog and digital
sections.
2.4 Clock Generator
The CS5541 includes an oscillator circuit which
can be connected with an external crystal to pro-
vide the master clock for the chip. The chip is de-
signed to operate using a low-cost 32.768 kHz
“tuning fork” type crystal. One lead of the crystal
should be connected to OSC1 and the other to
OSC2. A 10 Megohm resistor should be connected
in parallel with the crystal. Lead lengths should be
minimized to reduce stray capacitance. The con-
verter will operate with an external (CMOS com-
patible) clock applied at OSC1 with frequencies up
to 40 kHz.
2.5 Serial Port Interface
The CS5541’s serial interface consists of four con-
trol lines: CS, SDI, SDO, and SCLK.
CS, Chip Select, is the control line which enables
access to the serial port. If the CS pin is tied to logic
0, the port will function as a three wire interface.
SDI, Serial Data In, is the data signal used to trans-
fer data to the converters.
SDO, Serial Data Out, is the data signal used to
transfer output data from the converters. The SDO
output will be held at high impedance any time CS
is at logic 1.
SCLK, Serial Clock, is the serial bit-clock which
controls the shifting of data to or from the ADC’s
serial port. The CS pin must be held at logic 0 be-
fore SCLK transitions can be recognized by the
port logic. To accommodate opto-isolators SCLK
is designed with a Schmitt-trigger input.
OSC2
VD+
VA+
VREF+
VREF-
DGND
AIN1+
SCLK
SDO
SDI
CS5541
OSC1
CS
+3.0 V
Analog
16
15
3
1
11
9
8
7
6
10
5
12
Optional Clock
Source
Serial
Data
Interface
5 kHz ~ 40 kHz
AIN1-
4
VA-
2
0.1
µF
0.1
µF
10
Ω
AIN2+
AIN2-
+
-
Voltage
Reference
14
13
Analog
Signal
Sources
Supply
10 M
Ω
Figure 9. CS5541 Configured with +3.0 V Analog Supply.



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