CS5541

8

DS500PP1

Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 40 kHz can be used for

increased throughput.

21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

22. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an

external clock source.

Parameter

Symbol

Min

Typ

Max

Units

Master Clock Frequency:

External Clock

Internal Oscillator (Note 20)

MCLK

5

-

-

32.768

40

-

kHz

Master Clock Duty Cycle

40

-

60

%

Rise Times

(Note 21)

Any Digital Input Except SCLK

SCLK

Any Digital Output

-

-

-

-

-

50

1.0

100

-

µs

µs

ns

Fall Times

(Note 21)

Any Digital Input Except SCLK

SCLK

Any Digital Output

-

-

-

-

-

50

1.0

100

-

µs

µs

ns

Start-up

Oscillator Start-up Time

XTAL = 32.768 kHz (Note 22)

-500

-

ms

Power-on-Reset Period

-490

-

MCLK

cycles

Serial Port Timing

Serial Clock Frequency

SCLK

0

-

2

MHz

Serial Clock

Pulse Width High

Pulse Width Low

250

250

-

-

-

-

ns

ns

SDI Write Timing

CS Enable to SCLK Rising

50

-

-

ns

Data Set-up Time prior to SCLK rising

50

-

-

ns

Data Hold Time After SCLK Rising

100

-

-

ns

SCLK Falling Prior to CS Disable

100

-

-

ns

SDO Read Timing

CS to Data Valid

--

150

ns

SCLK Falling to New Data Bit

--

150

ns

CS Rising to SDO Hi-Z

--

150

ns